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Published byMoris Richards Modified over 9 years ago
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1 Part III Packet Transmission Chapter 7 Packets, Frames, and Error Detection
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2 Scope Discuss the concept of packet Explain how a sender and receiver coordinate to transfer a packet Show how packet can be implemented in a character-oriented network using a simple frame format Discuss mechanisms used for error detection
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3 The Problem Cannot afford individual network connection per pair of computers Reasons Installing wires consumes time and money Maintaining wires consumes money (esp. long- distance connections) C(N,2)=N(N-1)/2
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4 Solution Network has Shared central core Many attached stations Problems Some applications have large transfers Some applications cannot wait (e.g., interactive) Need mechanism for fairness Quality of Service (QoS) guarantee
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5 Packet Switching Principle Solution for fairness Divide data into small units called packets, which it sends individually Packet (switching) networks Allow each station opportunity to send a packet before any station sends another Form of time-division multiplexing
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6 Illustration of Packet Switching
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7 Packets and Hardware Frames Each H.W. technology defines the details of packets that can be transfer on that H.W. Format Minimum / maximum size Hardware packet called a frame
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8 Example Frame Format Used with RS-232 RS-232 is character-oriented permits arbitrary delay between characters Special characters (i.e., unused character in a text document) are picked as frame delimits Start of header ( soh )(e.g., ^) End of text ( eot )(e.g., ~)
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9 When Data Contains Special Characters Translate to alternative form by inserting extra bits or bytes Called byte stuffing Example
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10 Illustration of Frame With Byte Stuffing Stuffed frame longer than original Necessary evil
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11 Transmission Errors Interference can change signal used for transmission Bits lost Bit values changed Unsent data to appear Frame includes additional information to detect / correct error Set by sender Checked by receiver Statistical guarantee
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12 Error Detection And Recovery Techniques (1) Parity bit One additional bit per character Can use Even parity Odd parity Cannot handle error that changes two bits 1011011 1011011 1 1010011 1 (1-bit error) 1110011 1 (2-bit error)
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13 Error Detection And Recovery Techniques (2) Checksum Computation Example Checksum appended to frame Handles multiple bit errors Cannot handle all errors
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14 Error Detection And Recovery Techniques (2) Illustration Of Errors: Checksum Fails to Detect Second bit reversed in each item
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15 Error Detection And Recovery Techniques (3) Cyclic Redundancy Check ( CRC ) Mathematical function for data More complex to compute Detect more errors than a checksum CRC covers data only
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16 Building Blocks For CRC Exclusive or Shift register
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17 Example Of CRC Hardware Computes the 16-bit CRC Registers initialized to zero Bits of message shifted in one at a time CRC for the message found in registers A receiver calculates the CRC for an incoming message
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18 Example CRC Computation 若欲傳送資料 10 ,試計算其 CRC 值 0 xxx 000000000000000 1 0 xxx 000000000000000 0 00 00 1 100 0 xxx 000000000 1 00000 First bit:
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19 Second bit: Example CRC Computation (ctn.) 0 xxx 000000000 1 00000 0 0 xxx 000000000 1 00000 0 000 0 0000 0 xxx 000000001 0 00000
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20 Exercise What is the content of register?
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21 The End
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22 Example CRC Computation 0 + 3210 Power of x Incoming bit string 11000001010Initial 000 + 1 + 0001010step 0 100 + 0 + 001010step 1 001 + 0 + 01010step 2 010 + 0 + 1010step 3 100 + 1 + 010step 4 001 + 1 + 1010step 5 011 + 1 + 0step 6 110 + 0 + step 7 101 + + Exclusive OR 1 1 0 0 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1 0 1 1 1 0 0 1 1 0 0 1 0 1 0 step1 step7 step2 step3 step4 step5 step6
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23 Error Detection And Recovery Techniques (3) CRC Arithmetic Background X 4 +X 3 +1 X 10 +X 9 +X 7 +X 5 +X 4 X 6 +X 3 +X X 10 +X 9 +X 6 +X 7 +X 6 +X 5 +X 4 +X 7 +X 6 +X 3 X 5 +X 4 +X 3 X 5 +X 4 +X X 3 +X remainder 1 1 0 1 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 0 remainder 1 0 1 0 0+0=00-0=0 1+0=11-0=1 0+1=10-1=1 1+1=01-1=0
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24 Error Detection And Recovery Techniques (3) How CRC Works Sending Given the generator polynomial G(x) B(x): sending bit string+ n “0”s (degree of G(x)) R(x): remainder T(x): B(x) - R(x) Receiving G(x) | T’(x) T’(x) T(x) G(x) | T’(x) T’(x) T(x) 1 1 0 1 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 0 remainder 1 0 1 0
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25 Error Detection And Recovery Techniques (3) CRC Example 1 1 0 1 0 1 1 1 0 1 0 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 0 1 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 remainder Correct! 1 1 0 0 1 1 0 0 1 0 1 0 1 1 0 0 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1 0 1 remainder Incorrect! 1 1 0 0 1 1 0 0 1 0 1 0
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