1. IEEE 1394 A high-speed computer I/O serial bus CASI / ELEC 98 By Rachad ALAO Ecole Nationale Supérieure des Télécommunications ralao@venus.org

2. PC Video Camera DVD - RAM IEEE 1394, by Rachad ALAO ( ralao@venus.org )ralao@venus.org What’s the best way to interconnect these devices ?

3. PC Video Camera DVD - RAM IEEE 1394, by Rachad ALAO ( ralao@venus.org )ralao@venus.org What’s the best way to interconnect these devices ? Why not with USB?Too slow! Why not with a SCSI bus?Fast enough, but… What about an IEEE 1394 bus?You’ve got it! Isochronous Traffic. Bandwidth Requirement : 6Mbit/s Sporadic traffic. Bandwidth Requirement : 16Mbit/s

4. IEEE 1394 Lecture Plan IEEE 1394, by Rachad ALAO ( ralao@venus.org )ralao@venus.org I. How does IEEE 1394 work ? Overview Topology Type of Transaction Protocol’s Structure Example of Data Transfer II. Architecture of a IEEE 1394 ControllerII. Architecture of a IEEE 1394 Controller. Project Overview Functional Block Overview Block Level Detailed Architecture Transaction Layer, driver. III. Conclusion.

5. How does IEEE 1394 work ? Overview IEEE 1394, by Rachad ALAO ( ralao@venus.org )ralao@venus.org  Back to Lecture Plan High Speed Hot plug and play Isochronous capable “Memory-bus-like” logical architecture

6. How does IEEE 1394 work ? Topology IEEE 1394, by Rachad ALAO ( ralao@venus.org )ralao@venus.org  Back to Lecture Plan Physical topology is a non-cyclic network but Logical Topology is a bus. Node_ID[ 15.. 0] = Bus_ID[15.. 6] || Physical_ID[ 5.. 0]

7. How does IEEE 1394 work ? Type of Transaction IEEE 1394, by Rachad ALAO ( ralao@venus.org )ralao@venus.org  Back to Lecture Plan Different type of subaction : Asynchronous subaction Asynchronous broadcast subaction Isochronous subaction Different part of a subaction : Arbitration sequence Data packet Acknowledgment Typical structure of a data packet

8. How does IEEE 1394 work ? Protocol’s Structure IEEE 1394, by Rachad ALAO ( ralao@venus.org )ralao@venus.org  Back to Lecture Plan Different managers needed : ROOT ( Arbiter ) CYCLE_MASTER ISOCHRONOUS MANAGER BUS MANAGER

9. How does IEEE 1394 work ? Example of Data Transfer 1 IEEE 1394, by Rachad ALAO ( ralao@venus.org )ralao@venus.org  Back to Lecture Plan PC Root Isochronous Manager Bus Manager Cycle Master Node_ID = 3 Video Camera Node_ID = 1 DVD - RAM Node_ID = 2

10. How does IEEE 1394 work ? Example of Data Transfer 2 IEEE 1394, by Rachad ALAO ( ralao@venus.org )ralao@venus.org  Back to Lecture Plan Cycle_StartCh. iCh. j Isochronous Gap Subaction Gap Cycle_StartCh. iCh. j Arbitration Data Packet TX_DATA_END Cycle_StartCh. iCh. jData Packet Acknowledge Gap Acknowledge Packet Step 1 : Step 2, 3, 4 : Step 5 : DVD RAM want to perform a write data block transaction to the PC

11. How does IEEE 1394 work ? Example of Data Transfer 3 IEEE 1394, by Rachad ALAO ( ralao@venus.org )ralao@venus.org  Back to Lecture Plan Step 1 : Step 2, 3, 4 : Camera sends MPEG2 data to the PC at a 6 Mbit/s fixed rate. Cycle_Start Isochronous Gap Cycle_Start Arbitration Ch. K Data Packet TX_DATA_END Prior to all its isochronous transfers, the camera must allocates bandwidth and channel.

12. Architecture of a IEEE 1394 Controller Project Overview IEEE 1394, by Rachad ALAO ( ralao@venus.org )ralao@venus.org  Back to Lecture Plan

13. Architecture of a IEEE 1394 Controller Functional Block Overview IEEE 1394, by Rachad ALAO ( ralao@venus.org )ralao@venus.org  Back to Lecture Plan TPA TPB Power Phy Layer Link Layer FIFO Controller Local Host Bus Adapter * Receive Transmit_Granted Hold Link_request Link_DS R/W Add[7..0] Link_Data[7..0] Clk ( 50 Mhz ) Link_On Power_Down /Reset Phy_DS Phy_Data[7..0] Host_DS R/W Host_Add[7..0] Host_Data[31..0] FIFO_DS FIFO_Data[31..0] Clk ( 33 Mhz ) /Reset INT * Local Bus Adapter Interface is Bus Dependent! No generic interface can be given. Clk ( 50 Mhz ) /Reset FIFO_DS FIFO_R/W FIFO_Add[7..0] FIFO_Data[31..0] Link_DS Link_Data[31..0] Link_Add[2..0] Link_R/W Transaction layer and part of the bus management will be software components ( driver )

14. Architecture of a IEEE 1394 Controller Block Level Detailed Architecture - PHY IEEE 1394, by Rachad ALAO ( ralao@venus.org )ralao@venus.org  Back to Lecture Plan Phy State Machine & Internal Regs Receive Data Decoder Transmit Data Encoder Cable Analog Interface Receive Transmit_Granted Hold Link_request Link_DS R/W Add[7..0] Link_Data[7..0] Clk ( 50 Mhz ) Link_On Power_Down /Reset Phy_DS Phy_Data[7..0] TPA TPB Power

15. Architecture of a IEEE 1394 Controller Block Level Detailed Architecture - LINK IEEE 1394, by Rachad ALAO ( ralao@venus.org )ralao@venus.org  Back to Lecture Plan Receive Transmit_Granted Hold Link_request Link_DS R/W Add[7..0] Link_Data[7..0] Clk ( 50 Mhz ) Link_On Power_Down /Reset Phy_DS Phy_Data[7..0] Clk ( 50 Mhz ) /Reset FIFO_DS FIFO_R/W FIFO_Add[7..0] FIFO_Data[31..0] Link_DS Link_Data[31..0] Link_Add[2..0] Phy Interface Transmitter Receiver CRC Isoch. Manager Isoch. Monitor Link State Machine and Registers Link_R/W

16. Architecture of a IEEE 1394 Controller Block Level Detailed Architecture - FIFO IEEE 1394, by Rachad ALAO ( ralao@venus.org )ralao@venus.org  Back to Lecture Plan Host Adapter Interface FIFO Controller &Internal Regs Link Layer Interface General Receive FIFO Asynch. Transmit FIFO Isoch. Transmit FIFO Host_DS R/W Host_Add[7..0] Host_Data[31..0] FIFO_DS FIFO_Data[31..0] Clk ( 33 Mhz ) /Reset INT Clk ( 50 Mhz ) /Reset FIFO_DS FIFO_R/W FIFO_Add[7..0] FIFO_Data[31..0] Link_DS Link_Data[31..0] Link_Add[2..0] Link_R/W

17. Architecture of a IEEE 1394 Controller Transaction Layer, driver IEEE 1394, by Rachad ALAO ( ralao@venus.org )ralao@venus.org  Back to Lecture Plan The Transaction layer and part of the bus management functions must be software components. Transaction layer must implement Read, Write and Lock transaction. Driver must offer ability to handle isochronous transfer. Driver must be IRQ driven and able to initiate DMA transfers. Driver model will depend on the target application OS.

18. Conclusion IEEE 1394, by Rachad ALAO ( ralao@venus.org )ralao@venus.org  Back to Lecture Plan Objectives : Give a synthesis of the IEEE 1394 Bus standard Give a Hardware Specifications of an IEEE 1394 Solution Constitute a good starting for the development of an IEEE 1394 Solution Reached ! + Gave me a good understanding of the IEEE 1394 Protocol - Showed me the difficulty to build specifications from a complex standard - No multicast for asynchronous packets! Surprising for such a complicated standard.