1. 1 OUTPUT Pad and Driver

2. 2 CLOCK DRIVER

3. 3 Buffering S = scaling or tapering factor CL = S N+1 Cg ……………… All inverters have identical delay of t o = delay of the first stage (load =Cd+Cg)

4. 4 Buffering 0 1 2 3 3 4 5 Cd/Cg S If the diffusion capacitance Cd is neglected, S = e = 2.7

5. 5 Layout of Large Device

6. 6 Large Transistor Layout

7. 7 Output Drivers Standard CMOS Driver Open Drain/Source Driver: Single Transistors Tri-state Driver Bi-directional Circuit

8. 8 Tri-state Driver u Tri-state or High impedance u Used to drive internal or external busses u Two inputs: Data In and Enable u Various signal assertions u Two types: C 2 MOS CMOS with Control Logic C 2 MOS

9. 9 V DD En PAD Out In Control logic could be modified to obtain Inversion/non-inversion Active low/high Enable For large load, pre-drivers are required Tri-state Driver

10. 10 Latch-up: Trigger Factors which trigger latch-up u transmission line reflections or ringing u voltage drop on the VDD bus u “hot plug in” of unpowered circuit board u electrostatic discharge u sudden transient on power and ground busses u leakage current across the junction u radiation: x-ray, cosmic

11. 11 Input PAD

12. 12 Protection Circuitry Principles Punch Through Avalanche

13. 13 Protection Circuitry

14. 14 Protection Circuitry

15. 15 Input protection u Electrostatic discharge can take place through transfer of charges from the human body to the device. u Human body can carry up to 8000V. u Discharge can happen within hundreds of nanoseconds. u Critical field for SiO2 is about 7X106 V/cm. u For 0.5u CMOS process the gate oxide can withstand around 8V u Some protection technique is required with minimum impact on performance DUT 100pF 1.5K  1M  Vesd Human Body model

16. 16 ESD Structures Basic technique is to include series resistance and two clamping diodes. The resistance R is to limit the current and to slow down the high voltage transitions. R could be polysilicon or diffusion resistance Diffusion resistance could be part of the diode structure Typical values of R: 500 to 1k PAD VDD R

17. 17 Layout of ESD Structure p+ n+ p+ Guard Ring PAD This structure uses transistors as clamping diodes

18. 18 p+ n+ p+ Guard Ring PAD VDD GND Layout of ESD Structure

19. 19 Another ESD Structure PAD VDD R2 Thick FOX MOS Transistor R1

20. 20 Bi-direct PAD PAD V DD ESD ProtectionInput Buffer Control Logic EN IN Pre-drivers

21. 21 Thank you !