1. Measurements of the first ON Semiconductor production wafers at Udine Prepared by Diego Cauz on behalf of the group of Udine April 2004 Udine

2. Atlas Pixel Italia Apr 20042 Measurement speed-up Doctor Sergey Gorokhov is back in Udine since April 14th. He will stay for 3 months

3. Atlas Pixel Italia Apr 20043 ON-Semic wafers in Udine We have received 11 ON Semiconductor wafers in April: –2 partially measured for quick shipping to AMS

4. Atlas Pixel Italia Apr 20044 Visual inspection (VIS)(1/3) 9688-07Y-Y correct 9688-10Y-Y correct 9688-15Y-Y correct 9688-18Y-Y correct 9688-21Y-Y correct Mask Align (H-V) Wafer n-side L n-side R p-side L p-side R ID marking

5. Atlas Pixel Italia Apr 20045 Visual inspection (VIS)(2/3) 1201-07Y-Y correct 1201-10Y-Y correct 1203-11Y-Y correct 1203-26Y-Y correct 1203-27Y-Y correct 1203-34Y-Y correct Mask Align (H-V) Wafer n-side L n-side R p-side L p-side R ID marking Bad passivation vernier in the 4th vernier pair on all 4 monitors, both H and V, all wafers. See next slide

6. Atlas Pixel Italia Apr 20046

7. 7 Many defects, probably scratches on the tiles of 9688-07 Tile 1: 8 scr.s -93 pix Tile 2: 4 scr.s -20 pix Tile 3: 9 scr.s -122 pix

8. Atlas Pixel Italia Apr 20048 Wetting residue

9. Atlas Pixel Italia Apr 20049 WaferVernier Passiv. Bump openings 9688-07badbad* 9688-10bad 9688-15bad 9688-18bad 9688-21bad WaferVernier Passiv. Bump openings 1201-07badgood 1201-10badgood 1203-11badgood 1203-26bad~good 1203-27bad~good 1203-34bad Visual inspection (VIS)(3/3) *: AMS communication ~: bad on limited areas

10. Atlas Pixel Italia Apr 200410 9688-10

11. Atlas Pixel Italia Apr 200411 1203-11

12. Atlas Pixel Italia Apr 200412 Thickness measurement (THI) 9688-07251252 9688-10254 0 9688-15253252+1 9688-18254253+1 9688-21253252+1 Wafer th1 th2  (  m) 220  m < th < 260  m  th < 10  m 1201-07253254 1201-10254253+1 1203-11253 0 1203-26254253+1 1203-27253252+1 1203-34253252+1 Wafer th1 th2  (  m)

13. Atlas Pixel Italia Apr 200413 I-V on diode w/ guard ring (IVD) 1201-075000.98 1201-104753.34 1203-114808.74 1203-263755.53 1203-275004.21 1203-345005.27 Wafer Vbd (V) Iop (nA) Iop = I(Vop)Vbd = max V(I < 25 nA) 9688-075002.01 9688-105001.33 9688-155000.99 9688-185001.48 9688-215002.20 Wafer Vbd (V) Iop (nA)

14. Atlas Pixel Italia Apr 200414 C-V on diode w/ guard ring (CVD) (1/2) Vdep Cdep Vop  Wafer (V) (pF) (V) (  cm) 30 < Vdep (V) < 1202000 <  (  cm) < 5000 Vdep = V(kink in C-V curve) Cdep = C(Vdep) Vop = max(150 V, Vdep + 50 V) 9688-0711541651850 9688-10954.71502290 9688-15954.81502250 9688-181304.01801660 9688-211053.31552040 Measurement very noisy. One cable found defective. Large incertitude on Vdep.

15. Atlas Pixel Italia Apr 200415 C-V on diode w/ guard ring (CVD) (2/2) Vdep Cdep Vop  Wafer (V) (pF) (V) (  cm) 30 < Vdep (V) < 1202000 <  (  cm) < 5000 Vdep = V(kink in C-V curve) Cdep = C(Vdep) Vop = max(150 V, Vdep + 50 V) 1201-071053.81552050 1201-10704.61503100 1203-111204.81701800 1203-261053.61552050 1203-27904.91502380 1203-34404.31505350 See next slide

16. Atlas Pixel Italia Apr 200416

17. Atlas Pixel Italia Apr 200417 I-V on tiles (1/2) Wafer Vop (V) Vbd (V) S good tiles Vbd > VopS = I(Vop) / I(Vop-50) < 2 9688-07165500 385 801.13 1.44 -1-2-x 9688-10150 85 500 230 - 1.21 4.08x-2-x 9688-15150500 75 5001.34 - 1.171-x-3 9688-18180500 500 751.15 1.15 -1-2-x 9688-21155295 500 701.80 1.12 -1-2-x

18. Atlas Pixel Italia Apr 200418 I-V on tiles (2/2) Wafer Vop (V) Vbd (V) S good tiles Vbd > VopS = I(Vop) / I(Vop-50) < 2 1201-07155500 500 751.23 1.23 -1-2-x 1201-10150455 500 701.15 1.15 -1-2-x 1203-11170310 75 2051.18 - 1.711-x-3 1203-26155265 310 701.77 1.21 -1-2-x 1203-27150145 345 8525.7 1.13 -x-x-x 1203-34150170 220 2057.27 1.63 3.21x-2-x Bad I-t

19. Atlas Pixel Italia Apr 200419 I-V on SC’s Vbd > VopS = I(Vop) / I(Vop-50) < 2 Wafer good/total Only half of the SC’s are being measured 9688-073/3 9688-103/3 9688-153/3 9688-183/3 9688-213/3 1201-073/3 1201-103/3 1203-113/4 1203-263/5 1203-273/3 1203-343/4 Wafer good/total

20. Atlas Pixel Italia Apr 200420 I-V on MC’s Vbd > VopS = I(Vop) / I(Vop-50) < 2 Wafer good/total Only half of the MC’s are being measured 9688-072/2 9688-102/2 9688-152/2 9688-182/2 9688-212/3 1201-072/2 1201-102/2 1203-112/2 1203-262/3 1203-272/2 1203-342/2 Wafer good/total

21. Atlas Pixel Italia Apr 200421 I-t on good tiles (ITS) Wafer-tile S S = Iend / Istart < 1.3 9688-07-011.06 1201-10-021.01 1203-27-02bad 1203-26-021.05

22. Atlas Pixel Italia Apr 200422 I-V on MOS (BOX) 9688-07100 9688-10100 Wafer Vbd (V) delay = 4 s Vbd = max V(I 50 V 1201-07100 1201-1096 1203-1180 1203-34100 Wafer Vbd (V)

23. Atlas Pixel Italia Apr 200423 C-V on MOS (COX) Wafer Cox (pF) Cmin (pF)C FB (pF) V FB (V) Cox = CmaxV FB = V(C nearest to C FB ) 9688-072734.856.816 9688-102788.052.38 1201-072657.354.14 1201-102675.746.112 1203-112739.957.514 1203-342698.536.44.5

24. Atlas Pixel Italia Apr 200424 I-V on gate-controlled diode (IVG) Itop = I(V FB +3 V) Ibot = I(V FB – 3 V) Wafer Itop (pA) Ibot (pA)Iox(pA) 9688-0788314869 9688-1021826192 1201-0741422392 1201-1051618498 1203-1178955734 1203-3426935234

25. VFB is around 16 V V FB is around 4 V COX, IVG discrepancy

26. Atlas Pixel Italia Apr 200426 I-Vg on MOSFET (MFE) Wafer Vth (V) p-dose (x 10 12 cm -2 ) 9688-07282.7 9688-10262.6 1201-07262.4 1201-10262.5 1203-11262.5 1203-34bad- 2.2 < p (10 12 cm -2 ) < 3.5Vth = max V(I 0 V th is usually good, but I beyond threshold is very low. See next slide.

27. Atlas Pixel Italia Apr 200427

28. Atlas Pixel Italia Apr 200428 Vpix-V on punch-thru structure (PUT) 9688-101.64 9688-152.09 9688-183.45 9688-212.53 Wafer Vpt (V) Vpt >3 V 1201-071.88 1201-101.75 1203-11bad 1203-262.37 1203-272.17 Wafer Vpt (V)

29. Atlas Pixel Italia Apr 200429 Conclusions 11 wafers are being measured –Missing measurements: VIS, PLA –Some measurements need to be done again Wafer quality : –bad passivation in the mask alignment monitor for all 4th vernier pair, wafers 9688-07, 1203-34 –Many scratches on the tiles of 9688-07 –Bad bump pads for 9688-10 (and 9688-07) –wafer 1203-34 does not pass MFE test –wafer 1203-34, 9688-10 have only one good tile –wafer 1203-27 has no good tile –Almost all wafers do not pass PUT test

30. Atlas Pixel Italia Apr 200430 Wafer acceptance reasons 9688-07* BO,  9688-10BO,PUT,1GT 9688-15BO,PUT 9688-18 BO,  9688-21BO,PUT Wafer acceptance reasons 1201-07PUT 1201-10PUT 1203-11 ,PUT 1203-26PUT 1203-27It,PUT,0GT 1203-34* ,1GT Conclusions

31. Atlas Pixel Italia Apr 200431 Project Progress Tracking Dortmund 145/250 58% New Mexico 0/250 0% Prague 250/250100% Udine 212/250 84% This tool is not trustable. Laboratorytiles meas/totalpercent

32. Atlas Pixel Italia Apr 200432 Tile pool In reality the 4 labs have received a total of 1121 tiles, 1060 of which have been accepted: –Dortmund:250 –NM:265 –Prague:250 –Udine:212 The missing tiles are to be finished measuring by Udine (14 wafers) and Dortmund.