1. 1 CMOS R&D for STAR Wieman RNC LBNL Snowmass Review of current R&D and technologies session SG3-1 Fri 18 August 2005 1:30-5:00 Pyramid Room

2. 2 Things to cover  Some work on a photo-gate, an attempted improvement on the CMOS pixels, understanding the problem  Forward bias diode, short decay time  Avalanche effect in APS, why no gain?  Projects in the pipe

3. 3 Y. Chen, S. Kleinfelder, A. Koohi, S. Li University of California, Irvine, California H. Huang, A. Tai University of California, Los Angeles, California 90095 V. Kushpil, M. Sumbera Nuclear Physics Institute AS CR, 250 68 Rez/Prague, Czech Republic C. Colledani, W. Dulinski, A. Himmi, C. Hu, A. Shabetai, M. Szelezniak, I. Valin, M. Winter Institut de Recherches Subatomique, Strasbourg, France F. Bieser, R. Gareus, L. Greiner, H.S. Matis, M. Oldenburg, H.G. Ritter, L. Pierpoint, F. Retiere, A. Rose, K. Schweda, E. Sichtermann, J.H. Thomas, H. Wieman, E. Yamamoto Lawrence Berkeley National Laboratory, Berkeley, California 94720 STAR CMOS R&D Participants

4. 4  With the standard CMOS pixel array off chip CDS is required to remove fixed pattern noise and KTC reset noise  In the standard CMOS pixel array the signal is spread over multiple diodes uPenalty in signal to noise  Potential advantages of photo-gate uUse like CCD – read voltage, transfer charge – read voltage again and take difference. Gives on chip CDS uIncrease signal by reducing signal spreading to adjacent pixels. The photo gate permits large geometry without adding capacitance to the sense node. Photo gate purpose – to address standard pixel limitations P- P P+ Standard diode geometry

5. 5 First silicon tests Photo-gate directly to sense node drain DC bias: V photo-gate 0.6 V V drain 2.4 V Accumulated histogram of output signal for Fe55 X-ray test after CDS correction  Signal spreading  Reduced gain Issues:

6. 6 Photo-gate LED test  Used a single pixel in sector 5 (simple structure with photo- gate and small drain on the edge) uPhoto-gate voltage 1 volt uDrain voltage set by full reset voltage  Test sequence uReset all pixels uClock row and column shift registers to select a single pixel uInject 2 red LED pulses uObserve output voltage with oscilloscope throughout sequence  Also did same test with sector 1 ( the standard diode) for comparison Sector 5 Photo-gate drain

7. 7 Measured output voltage Pulse 1 Pulse 2  Features to note uBoth sectors exposed to same LED pulses, but light attenuated for sector 1 uSector 5 response to 1 st LED pulse much smaller than to 2 nd uSector 5 leakage current ramp increases after 1 st LED pulse uResponse difference for the two pulses in sector 5 is directly related to gate, since sector 1 shows that readout structures are not affected differently by the two pulses uReducing the pulse separation did not change effect Standard pixel diode Photo-gate 200  s

8. 8 Photo-gate time response to two pulses the same, only amplitude difference Pulse 1 Pulse 2 Adjust amplitude and overlay Signal fits: + plus leakage slope   204  s

9. 9 Photo-gate  Test chip uMeasured charge transfer (200  s) uShows saturation effects  Has been suggested that surface states at the oxide silicon are the cause  Quantitative check of uTransfer delay uSaturation uLeakage current (large, another feature of the gate)

10. 10 Conditions under the gate in the p epi layer p - epi p - epi with n type drain In thermal equilibrium p silicon inverted with accumulation of electrons under the gate Addition of drain removes electrons leaving depleted region Depleted space charge region Field free region, saturated with mobile holes

11. 11 First step of electron collection Diffusing electrons caught in the vertical space charge field under the gate Gate Drain Electrons distribute along the surface

12. 12 Check of time constants for different processes tells if surface traps are a reasonable explanation for slow transfer Gate Drain I direct Direct drain current I trapped Trapping current I delayed Detrapping drain current Surface states dd Time constant for direct diffusion to the drain Time constant for capture by the traps Time constant for release from the traps rr cc If  d >  c will be trapped If  r is large transfer is delayed

13. 13 Simple diffusion transfer of electrons from gate to drain Diffusion equation in 1D Solve with COSMOS FEA (~3D) – thermal transient solution, analogous diffusion equation Result:  d = 120 ns Start with uniform temperature and a heat sink at the drain Convert to electron diffusion photo-gate drain total electrons under gate

14. 14 Energy window for contributing traps – how many traps Less than 100  s decay time Sze Traps already filled Decay time constant back to the conduction band, Zhang Li paper Number of contributing traps More than 15 ms decay time

15. 15 Time constants show delay  d = 120 ns  c = 75 ns  r = 100  s Capture time easy to calculate, depends on surface trap density, the vertical density profile of the electrons. Surface trap density from literature, determined from capacitance measured as a function of frequency Trap release time depends on trap energy relative to conduction band. Only counted traps with decay times > 100  s Capture time for 100  s traps is less than the direct diffusion time to the drain, so trap delay is expected. Diffusion time constant

16. 16 Number of empty traps is consistent with measured effects  10000 - The number of empty traps from the published densities which are empty and have a lifetime of more than 100  s uA trapping time ( 75 ns ), less than diffusion time uA consistent with saturation by the estimated 4000 photo generated electrons. Another reason why photo gate won’t work for us, our signals are too small to saturate the traps.

17. 17 Surface traps also explain large leakage current Calculated surface generated current using Reed Schockley Hall 32 fA Based on literature values of surface trap density and the width of the mid gap energy window contributing to thermally generated current Measured leakage 17 fA This large leakage current is another feature of the photo gate making it unsuitable for our application. Since, it appears that the surface traps are the problem, the only obvious solution for this approach is buried channels Close enough

18. 18 Forward bias diode, TSMC 0.25  m issue  MEMOSTAR design replaces reset FET with forward bias diode which acts as high impedance connection to Vdd. Restoring time constant after hit is long compared to frame read time.  Expected time constant based on diode equation and leakage current: 38 ms (consistent with AMS MIMOSAs)  Measured time constant with Kleinfelder APS3 (TSMC 0.25  m) 29  s ~1000 times too short, Confirms IReS experience with TSMC 0.25  m

19. 19 Avalanche gain, why not?  Output voltage of pixel diode. Droop is due to impact ionization in the source follower FET, S. Maestre et al.  Injected signal from 3 equal amplitude LED flashes  Microscopic view shows identical step size. Why no gain on the third pulse? Kleinfelder APS-3 sector 1

20. 20 Projects in process  0.5  m APS – planning beam tests to measure signal amplitude  Study of performance on diode size

21. 21 Photo gate summary  Some questions remain, but surface traps could explain photo-gate behavior uThey provide delay on right order uThey seem to have right number to see saturation effects uThey are consistent with observed leakage current  Note, both Turchetta and Janesick tell me they have tried and failed to make a working photo-gate in standard CMOS. Janesick saw the same type of delayed signal  Janesick has made photo-gates work using a special process from Jazz Semiconductor with buried channel -- big bucks  Will there eventually be a photo process that available to us with buried channel?

22. 22 STAR Micro Vertex Detector  Two layers u1.5 cm radius u4.5 cm radius  24 ladders u2 cm X 20 cm each u< 0.3% X 0 u~ 100 Mega Pixels Purpose: Greatly improve D meson capability in STAR

23. 23 Conceptual mechanical design

24. 24

25. 25 Drain current after light injection  Nano amp drain current  Rapid electron transfer - complete in 60 ns photo gate transfer gate drain Light injection 60 ns Simulation using SILVACO ATLAS running on laptop. Service through eecad, only a few 10s of dollars to run. About to change to per day cost of ~$170 Relied on Zhang Li and Wei Chen to get started

26. 26 photo gate source follower gate reset gate transfer gate row select gate sense node drain  Large photo-gate to collect large fraction of the charge on a single pixel, directly on the p- epi layer  Small transfer gate also directly on p- epi layer  Small drain (minimum capacitance) connected to source follower gate (sense node) Photo-gate geometry 20  m x -2  m- 1  m 5 nm 8  m 0.1  m 0.4  m P epi 1.4x10 15 1/cm 3 N+ 1x10 20 1/cm 3 photo gate transfer gate drain x = 0.4 and 0.8  m (simulation quantities) Chip designed and built by Stuart Kleinfelder and Yandong Chen UC Irvine

27. 27 Density of electrons at the surface left by LED transient layer of 4000 electrons left by LED signal under 20  m  20  m gate d y LED Integrate over volume under gate to get n s 1/e distance = 12 nm

28. 28 Rate of capture into surface states Capture to surface states faster than direct diffusion to drain therefore surface states will affect transfer rate  st = 75 ns <  n = 120 ns capturedirect diffusion Measured by C vs freq, see Sze Use number of empty traps