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Introduction to ABC Presenter: Shuo-Ren Lin Instructor: Jie-Hong Roland Jiang 2013/6/7 1.

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Presentation on theme: "Introduction to ABC Presenter: Shuo-Ren Lin Instructor: Jie-Hong Roland Jiang 2013/6/7 1."— Presentation transcript:

1 Introduction to ABC Presenter: Shuo-Ren Lin Instructor: Jie-Hong Roland Jiang 2013/6/7 1

2 Outline 0 Introduction 0 Basic data structure 0 Command summary 0 Customize ABC 0 Case study 2013/6/72

3 Introduction 0 A growing software system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs 2013/6/73

4 Growing? 2013/6/74

5 Basic Data Structure 2013/6/75 0 Type vs. functionality 0 http://www.eecs.berkeley.edu/~alanmi/abc/progra mming.pdf http://www.eecs.berkeley.edu/~alanmi/abc/progra mming.pdf Type/FunctionalitySOPBDDAND2Gates NetlistXXX Logic networkXXXX AIGX

6 Netlist 0 Nets, logic nodes, latches, PIs, and POs 0 A node can be represented using SOP or AIG, or gate from standard cell library 0 APIs (refer to abc.h) 0 Abc_NtkAlloc 0 Abc_NtkCreatePi, Abc_NtkCreatePo 0 Abc_NtkFindOrCreateNet 0 Abc_NtkCreateNode, Abc_NtkCreateLatch 0 Abc_ObjAddFanin 0 Abc_NtkFinalizeRead, Abc_NtkCheck 2013/6/76

7 Logic Network 0 A netlist, and the nets have been removed 0 Only PI/PO/latch/latch-input/latch-out names are saved (eliminate names of internal nodes) 0 APIs 0 Abc_NtkStartFrom 0 Abc_NtkForEachPi, Abc_NtkForEachCi, … 0 Abc_ObjPatchFanin, Abc_ObjTransferFanout 2013/6/77

8 AIG 0 Only contain 2-inputs AND and each fanin/fanout edge has an optional complemented attribute 0 APIs 0 Abc_AigAnd, Abc_AigOr, Abc_AigXor, … 0 Abc_AigReplace 2013/6/78

9 Logic Network vs. AIG 2013/6/79

10 Command Summary 2013/6/710

11 Command Summary -- Read 0 read_verilog 0 Support very limited subset of structural Verilog 0 read_blif 0 http://www1.cs.columbia.edu/~cs4861/s07- sis/blif/index.html http://www1.cs.columbia.edu/~cs4861/s07- sis/blif/index.html 0 read_aiger, read_bench, … 2013/6/711

12 Blif File Sample 2013/6/712

13 Command Summary -- Print 0 print_fanio 2013/6/713

14 Command Summary -- Print 0 print_level, print_supp 2013/6/714

15 Command Summary -- Print 0 print_io, print_stats 2013/6/715

16 Command Summary -- Comb. Synthesis 0 Combinational synthesis 0 AIGs 0 balance, refactor, rewrite, rr, renode, strash(structure hash) 0 BDDs 0 dsd, collapse 0 Logic network 0 cleanup, sweep 2013/6/716

17 Command Summary -- Comb. Synthesis 2013/6/717

18 Command Summary -- Verification 0 cec, sec, sat 2013/6/718

19 Command Summary -- Show 0 show 0 #node < 300 0 Install other software 0 GSview 0 Program for opening PostScript files 0 http://pages.cs.wisc.edu/~ghost/gsview/ http://pages.cs.wisc.edu/~ghost/gsview/ 0 GhostScript 0 Necessary script for Gsview 0 http://pages.cs.wisc.edu/~ghost/doc/GPL/ http://pages.cs.wisc.edu/~ghost/doc/GPL/ 0 Graphvis 0 Program for generate PostScript files 0 http://www.graphviz.org/ http://www.graphviz.org/ 2013/6/719

20 Command Summary -- Show 2013/6/720

21 Command Summary -- Tech. Mapping 0 map 0 Need genlib file (use command read_library) 0 Format: http://www.ece.cmu.edu/~ee760/760docs/genlib.pdf http://www.ece.cmu.edu/~ee760/760docs/genlib.pdf 2013/6/721

22 Command Summary -- Tech. Mapping 2013/6/722

23 Customize ABC 2013/6/723

24 Customize ABC 0 Three Steps 0 Declare command in abc.c 0 Implement command 0 Register command in function Abc_Init (in abc.c) 2013/6/724

25 Customize ABC: Step1 2013/6/725

26 Customize ABC: Step2 2013/6/726

27 Customize ABC: Step3 2013/6/727

28 Customize ABC: Finish 2013/6/728

29 Case Study: print_symmetry 0 Count symmetry input pair for each prime output 0 Use incremental SAT solving 0 Check the symmetry between x and y 2013/6/729 ≠ x y x y (ctrl + a + b) * (…

30 Basic Structure 2013/6/730 void Symmetry( Abc_Ntk_t * pNtk ) { Abc_Ntk_t * pNtk_temp; Abc_Obj_t * pCo; int i; Abc_NtkMakeComb( pNtk, 0); Abc_NtkForEachCo( pNtk, pCo, i) { pNtk_temp = Abc_NtkCreateCone( pNtk, Abc_ObjFanin0(pCo), Abc_ObjName(pCo), 0); pNtk_temp = Abc_NtkStrash( pNtk_temp, 0, 0, 0); //Compute Symm_CO nTotalSymm += Symm_CO; } printf("Total symmetry: %d\n",nTotalSymm); } pNtk pCo

31 Construct AIG Circuit 2013/6/731 pAig1 = (Aig_Man_t *) Abc_NtkToDar( pNtk_temp, 0, 0); pAig2 = (Aig_Man_t *) Abc_NtkToDar( pNtk_temp, 0, 0); pPi1 = ABC_ALLOC( Aig_Obj_t*, Aig_ManPiNum(pAig1)); pPi2 = ABC_ALLOC( Aig_Obj_t*, Aig_ManPiNum(pAig2)); pAig = Aig_ManStart( Aig_ManObjNumMax(pAig1) + Aig_ManObjNumMax(pAig2) ); // adding aig1 to aig Aig_ManConst1(pAig1)->pData = Aig_ManConst1(pAig); Aig_ManForEachPi( pAig1, pObj, j ) { pObj->pData = Aig_ObjCreatePi( pAig ); pPi1[j] = pObj->pData; } Aig_ManForEachNode( pAig1, pObj, j ) pObj->pData = Aig_And( pAig, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) ); // adding aig2 to aig // same as previous part //building exor miter pObj = Aig_Exor( pAig, Aig_ObjChild0Copy(Aig_ManPo(pAig1,0)),Aig_ObjChild0Copy(Aig_ManPo(pAig2,0)) ); Aig_ObjCreatePo( pAig, pObj ); Aig_ManCleanup(pAig); xor pAig1pAig2

32 Initialize CNF Manager nProblem = (Aig_ManPiNum(pAig1) - 1) * Aig_ManPiNum(pAig1) / 2; nLiterals = 1 + 7 * Aig_ManNodeNum(pAig) + Aig_ManPoNum(pAig) + 3 + nProblem * ( 8 + (Aig_ManPiNum(pAig1) - 2) * 6); nClauses = 1 + 3 * Aig_ManNodeNum(pAig) + Aig_ManPoNum(pAig) + 1 + nProblem * ( 4 + (Aig_ManPiNum(pAig1) - 2) * 2); pCnf = ABC_ALLOC( Cnf_Dat_t, 1 ); memset( pCnf, 0, sizeof(Cnf_Dat_t) ); pCnf->pMan = pAig; pCnf->nLiterals = nLiterals; pCnf->nClauses = nClauses; pCnf->pClauses = ABC_ALLOC( int *, nClauses + 1 ); pCnf->pClauses[0] = ABC_ALLOC( int, nLiterals ); pCnf->pClauses[nClauses] = pCnf->pClauses[0] + nLiterals; pCnf->pVarNums = ABC_ALLOC( int, Aig_ManObjNumMax(pAig) + nProblem ); 2013/6/732

33 Assign Variable for( l = 0 ; l < Aig_ManObjNumMax(pAig) + nProblem ; l++ ) pCnf->pVarNums[l] = -1; Number = 1; Aig_ManForEachPo( pAig, pObj, m) pCnf->pVarNums[pObj->Id] = Number++; Aig_ManForEachNode( pAig, pObj, m) pCnf->pVarNums[pObj->Id] = Number++; Aig_ManForEachPi( pAig, pObj, m) pCnf->pVarNums[pObj->Id] = Number++; pCnf->pVarNums[Aig_ManConst1(pAig)->Id] = Number++; l = 0; CtrlVar = ABC_ALLOC( int, nProblem); for( m = 0 ; m < Aig_ManObjNumMax(pAig) + nProblem ; m++) { if(pCnf->pVarNums[m] == -1) { CtrlVar[l] = m; l++; pCnf->pVarNums[m] = Number++; } pCnf->nVars = Number; 2013/6/733 3 4 5 1 2

34 Add Clauses of Nodes(ANDs) m = 0; Aig_ManForEachNode( pAig, pObj, m ) { OutVar = pCnf->pVarNums[ pObj->Id ]; pVars[0] = pCnf->pVarNums[ Aig_ObjFanin0(pObj)->Id ]; pVars[1] = pCnf->pVarNums[ Aig_ObjFanin1(pObj)->Id ]; // positive phase *pClas++ = pLits; *pLits++ = 2 * OutVar; *pLits++ = 2 * pVars[0] + !Aig_ObjFaninC0(pObj); *pLits++ = 2 * pVars[1] + !Aig_ObjFaninC1(pObj); // negative phase *pClas++ = pLits; *pLits++ = 2 * OutVar + 1; *pLits++ = 2 * pVars[0] + Aig_ObjFaninC0(pObj); *pClas++ = pLits; *pLits++ = 2 * OutVar + 1; *pLits++ = 2 * pVars[1] + Aig_ObjFaninC1(pObj); } 2013/6/734 sign Var. number

35 Incremental SAT-Solving pCtrl = ABC_ALLOC( lit, nProblem + 1); nTotalSymm_Po = 0; for( iProblem = 0 ; iProblem < nProblem ; iProblem++) { for( m = 0 ; m < nProblem ; m++ ) { if( m == iProblem ){ pCtrl[m] = lit_read((-1) * (pCnf->pVarNums[ CtrlVar[m] ] + 1)); } else { pCtrl[m] = lit_read((pCnf->pVarNums[ CtrlVar[m] ] + 1)); } pSat = (sat_solver *)Cnf_DataWriteIntoSolver( pCnf, 1, 0); if( pSat == NULL ) printf("WARNING SAT SOLVER IS NULL!\n"); stats = sat_solver_solve(pSat, &pCtrl[0], &pCtrl[nProblem], 10000000, 10000000, 0, 0); if( stats == l_False ) nTotalSymm_Po++; } 2013/6/735

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