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AUTOMATIC BUS PLANNER FOR DENSE PCBS Hui Kong, Tan Yan and Martin D.F. Wong Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign Form DAC2009
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Introduction Today, a high-performance PCB usually contains thousands of pins and more than ten signal layers. Such a problem scale makes manual design extremely time-consuming. Due to the high clock frequencies on modern PCBs, the routed nets must be subject to very stringent min-max length constraints which make the design even more difficult. typically take 2 months per board by manual design
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Internal Conflict Graph
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Problem Formulation Inputs: 1. number of routing layers 2. a set of bus intervals (min-max length constraint) 3. bus internal conflict graph Outputs: the layer assignment of the topological routes of buses Constraints: 1. max-min length constraint 2. each bus is routed in planar fashion considering crossing
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Flow Chart 1. Global routing, which routes all buses on a single layer with all routing resources mapped onto one layer. 2. Layer assignment of the routed bus. 3. Iterative improvement by reassignment and rerouting.
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Global Routing Hanan Grid cell
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Global Routing Dynamic Routing Graph
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Global Routing Example b1 b2 b3 Internal Conflict Graph
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Global Routing Critical Cut: the congestion may happen on Critical Cuts, so we need to estimate their congestion. V
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Global Routing Congestion Estimation Traditional Bin-packing based Max(0, 20*4+15 – 2*50 ) = 0 Max(0, 3-2) = 1
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Global Routing Negotiated-Congestion Routing: It rips up and reroutes buses iteratively. In each iteration, each bus is ripped up and rerouted once by following the same ordering. When routing a bus b, the router is to find a minimum cost path on the routing graph.
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Layer Assignment Use SA to solve layer assignment Initial solution is random assignment. Perturbation: move bus within each layer Cost: Intersection Cost + Congestion Cost
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Iterative Improvement If routing conflicts still exist, we perform a bubble- sort-like iterative improvement.
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Experimental Result A PCB form industry that has 7000+ nets and 12 routing layers and has been manually routed. Use layer assignment extracted form the manual solution
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Experimental Result Compare with manual solution
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Conclusion This paper we use a dynamic routing graph to guide the efficient search of planar topologies of the bus routes and a bin-packing-based congestion estimation to effectively avoid violations of routing capacity constraints. Finally, use a bubble-sort-like iterative improvement to further increase the number of routed nets.
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