1. PEDS: A PARALLEL ERROR DETECTION SCHEME FOR TCAM DEVICES Author: Anat Bremler-Barr, David Hay, Danny Hendler and Ron M. Roth Publisher/Conf.: IEEE INFOCOM 2009 Speaker: Han-Jhen Guo Date: 2009.03.25 1

2. OUTLINE Introduction The Proposed Scheme Basic idea PEDS architecture Hardware design (with mod-2 counters) Performance 2

3. INTRODUCTION Problem statement (search key = 1101) false miss/hit indirect false hit 3

4. The Proposed Scheme - Basic idea Assume that only one error can occur in each pair of symbols For each clause in the TCAM memory (eg. 0*10) 1. encoding to a pair with the check bit(s) eg. 00**1100 2. applying a sequence of TCAM searches for a predetermined set of search keys eg. predetermined set = {*…*01*…*, *…*10*…*}) 3. analyzing their results from step 2. there occurs 2 matches → no error (** is matched) there occurs no match → no error (00 or 11 is matched) there occurs 1 match only → ERROR! 4

5. The Proposed Scheme - Basic idea eg. check entry = *10* 5 ** 11 00 ** 01 ** ** ** (m) 10 ** ** ** (m) ** 11 00 ** ** 01 ** ** (n) ** 10 ** ** (n) ** 11 00 ** ** ** 01 ** (n) ** ** 10 ** (n) ** 11 00 ** ** ** ** 01 (m) ** ** ** 10 (m)

6. The Proposed Scheme - Basic idea eg. check entry = *10* with errors 6 ** 11 01 0* 01 ** ** ** (m) 10 ** ** ** (m) ** 11 01 0* ** 01 ** ** (n) ** 10 ** ** (n) ** 11 01 0* ** ** 01 ** (m) ** ** 10 ** (n) ** 11 01 0* ** ** ** 01 (m) ** ** ** 10 (n) ERROR!

7. THE PROPOSED SCHEME - PEDS ARCHITECTURE High-level PEDS architecture the i-th clause contains all the symbols whose indices modulo k equal i. 7

8. THE PROPOSED SCHEME - PEDS ARCHITECTURE (eg. of TCAM memory) check each of the W/k clauses (in conjunction with its check symbols) separately—but concurrently for all entries—against a predetermined set of search keys 8

9. THE PROPOSED SCHEME - PEDS ARCHITECTURE High-level PEDS architecture property of predetermined set of search keys an entry is error free if and only if the number of search keys that match it is in a predetermined set T (int. set) eg. T = {0, 2} 9 hardware-based mechanism counts the number of matches per entry and determines whether it belongs to T hardware-based mechanism counts the number of matches per entry and determines whether it belongs to T

10. The Proposed Scheme - Hardware design (with mod-2 counters) 1. Regard the 3 symbols “0”, “1”, and “*” as elements of the finite field of three elements, GF(3). Mapping: *  0; 0  +1; 1  -1 2. Encode each k -symbol clause into an n -symbol block in every entry (each block is a codeword of C ) fix the linear [n; k; d] code C over GF(3) d is the minimum (Hamming) distance between any two distinct codewords in C, that is, every two codewords in C differ in at least d positions (and there are two codewords that differ in exactly d positions). can detect any pattern of less than d errors that occur in codewords of C, including changes to and from “*” 10

11. The Proposed Scheme - Hardware design (with mod-2 counters) eg. C = {(-1, -1), (0, 0), (+1, +1)} d = 2 11

12. THE PROPOSED SCHEME - HARDWARE DESIGN (WITH MOD-2 COUNTERS) 3. Find the parity-check matrix H of C H is a right kernel of C eg., → r = 3 4. Find the L(h i ) eg. 12

13. THE PROPOSED SCHEME - HARDWARE DESIGN (WITH MOD-2 COUNTERS) 5. Decode for locating the erroneous entries Theorem - Let the k -symbol clauses in the TCAM be encoded into n -symbol blocks such that each block is a codeword of a linear [n; k; d] code C over F, and let h 1, h 2,…, h r be the rows of a parity-check matrix of C. Suppose that each block is subject to less than d errors. Then the following two conditions are equivalent for every block v in the TCAM: v is error-free. For every i = 1, 2, …, r, the number of vectors in L(h i ) that match v is even. 13

14. THE PROPOSED SCHEME - HARDWARE DESIGN (WITH MOD-2 COUNTERS) Hardware change required for implementing the fast detection scheme described above. ⊕ denotes a XOR gate □ denotes a 1-bit flip-flop 14

15. THE PROPOSED SCHEME - HARDWARE DESIGN (WITH MOD-2 COUNTERS) eg. 15 Flag as erroneous all TCAM entries whose match lines feed “1” to the priority encoder

16. THE PROPOSED SCHEME - HARDWARE DESIGN (WITH MOD-2 COUNTERS) eg. 16

17. THE PROPOSED SCHEME - HARDWARE DESIGN (WITH MOD-2 COUNTERS) eg. 17 Flag as erroneous all TCAM entries whose match lines feed “1” to the priority encoder

18. THE PROPOSED SCHEME - HARDWARE DESIGN (WITH MOD-2 COUNTERS) eg. 18 Flag as erroneous all TCAM entries whose match lines feed “1” to the priority encoder

19. PERFORMANCE The parameter k defines a trade-off when d is fixed resilience since the number of detectable errors per block is fixed, a poorer error rate requires using a smaller k space the number of check symbols per entry is proportional to the number W / k of blocks (clauses) per entry and, therefore, it reduces as k increases time the number of search keys that are applied during the decoding increases (exponentially) with k 19

20. PERFORMANCE The trade-off between the space and time assuming that the parity code is used (d = 2) with 100 information symbols (W = 100) 20 setting k to 3, 4, or 5 is the most practical choice

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