1. CS/EE 3700 : Fundamentals of Digital System Design
Chris J. Myers
Lecture 3: Implementation Technology
Chapter 3

2. Figure 3.1 Logic values as voltage levels

3. Figure 3.2 NMOS transistor as a switchx
= "low" x
= "high"
(a) A simple switch controlled by the input x
Gate
Source
Drain
Substrate (Body)
(b) NMOS transistor V G V V S D
(c) Simplified symbol for an NMOS transistor
Figure NMOS transistor as a switch

4. Figure 3.3 PMOS transistor as a switchx
= "high" x
= "low"
(a) A switch with the opposite behavior of Figure 3.2 a
Gate
Drain
Source V DD
Substrate (Body)
(b) PMOS transistor V G V V S D
(c) Simplified symbol for an PMOS transistor
Figure PMOS transistor as a switch

5. Figure 3.4 NMOS and PMOS transistors in logic circuitsV D V
= 0 V V D D V G V
= 0 V S
Closed switch
Open switch
when V = V
when V
= 0 V G DD G
(a) NMOS transistor V = V V V S DD DD DD V G V V V = V D D D DD
Open switch
Closed switch
when V = V
when V
= 0 V G DD G
(b) PMOS transistor
Figure NMOS and PMOS transistors in logic circuits

6. Figure 3.5 A NOT gate built using NMOS technologyV DD R R +
5 V - V V f f V V x x
(a) Circuit diagram
(b) Simplified circuit diagram x f x f
(c) Graphical symbols
Figure A NOT gate built using NMOS technology

7. Figure 3.6 NMOS realization of a NAND gateV DD V f V x 1 x x f 1 2 1 V x 2 1 1 1 1 1 1
(a) Circuit
(b) Truth table x x 1 1 f f x x 2 2
(c) Graphical symbols
Figure NMOS realization of a NAND gate

8. Figure 3.7 NMOS realization of a NOR gate

9. Figure 3.8 NMOS realization of an AND gateV V DD DD V f A V x 1 x x f 1 2 V x 2 1 1 1 1 1
(a) Circuit
(b) Truth table x x 1 1 f f x x 2 2
(c) Graphical symbols
Figure NMOS realization of an AND gate

10. Figure 3.9 NMOS realization of an OR gate

11. Figure 3.10 Structure of an NMOS circuit

12. Figure 3.11 Structure of a CMOS circuit

13. Figure 3.12 CMOS realization of a NOT gateV DD T 1 V V x f x T T f 1 2 T 2 on
off 1 1
off on
(a) Circuit
(b) Truth table and transistor states
Figure CMOS realization of a NOT gate

14. Figure 3.13 CMOS realization of a NAND gate
Find PUN and PDN using DeMorgan’s law
Figure CMOS realization of a NAND gate

15. Figure 3.14 CMOS realization of a NOR gate
Find PUN and PDN using DeMorgan’s law
Figure CMOS realization of a NOR gate

16. Figure 3.15 CMOS realization of an AND gate

17. Figure 3.16 A CMOS complex gate
f = x1’ + x2’ x3’
Figure A CMOS complex gate

18. Figure 3.17 A CMOS complex gate
f = x1’ + (x2’ + x3’) x4’
Figure A CMOS complex gate

19. Figure 3.18 Voltage levels in a CMOS circuit

20. Figure 3.19 Interpretation of voltage levelsx x f 1 2 1 x 1 1 1 f x 2 1 1 V V V x x f 1 2 1 1 L L H L H H
(b) Positive logic truth table and gate symbol H L H H H L x x f 1 2
(a) Voltage levels 1 1 x 1 1 f x 2 1 1
(c) Negative logic truth table and gate symbol
Figure Interpretation of voltage levels

21. Figure 3.20 Interpretation of voltage levelsx x f 1 2 x 1 1 f x 2 1 V V V x x f 1 1 1 1 2 L L L L H L
(b) Positive logic H L L H H H x x f 1 2
(a) Voltage levels 1 1 1 x 1 1 1 f x 1 1 2
(c) Negative logic
Figure Interpretation of voltage levels

22. Figure 3.43 a NMOS transistor when turned offV = V G
SiO 2 V = V S V D
++++++
++++
++++++
++++++
+++
++++++
++++++
++++++
++++++
++++++
++++++
++++++
Substrate (type p)
Source (type n)
Drain (type n)
(a) When V
= 0 V, the transistor is off GS
Figure 3.43 a NMOS transistor when turned off

23. Figure 3.43 b NMOS transistor when turned onV DD V = 5 V G
SiO 2 V = V S V = V D
++++++
++++
+++
++++++
++++++
++++++ ++
Channel (type n)
(b) When V
= 5 V, the transistor is on GS
Figure 3.43 b NMOS transistor when turned on

24. Figure 3.44 Current-voltage relationship in the NMOS transistorD
Triode
Saturation
ID = kn’ W/L [ (VGS – VT)VDS – ½ VDS^2]
ID = ½ kn’ W/L (VGS – VT)^2 V – V GS T V DS
Figure Current-voltage relationship in the NMOS transistor

25. Figure 3.45 Voltage levels in the NMOS inverterDD DD R V f I V = V
stat f OL V R x DS
RDS = VDS / ID = 1/ [kn’ W/L (VGS – VT)]
Vf = VDD RDS / (RDS + R)
See examples 3.4 and 3.5
(a) NMOS NOT gate
(b) V
= 5 V x
Figure Voltage levels in the NMOS inverter

26. Figure 3.46 Voltage transfer characteristics for the CMOS inverter= V OH DD
Slope = – 1 V = V OL V V V ( V – V ) V T IL IH DD T DD V x V — DD 2
Figure Voltage transfer characteristics for the CMOS inverter

27. (a) A NOT gate driving another NOT gate1 2 A x f
(a) A NOT gate driving another NOT gate
NML = VIL – VOL
NMH = VOH - VIH

28. Figure 3.47 Parasitic capacitance in integrated circuits
tp = C dV / ID = C Vdd/2 / ID = 1.7C / kn’ W/L Vdd
Figure Parasitic capacitance in integrated circuits

29. Figure 3.48 Voltage waveforms for logic gates

30. Figure 3.49 Transistor sizes

31. V V R V I V = V V R V = 5 V V T V V T DD DD f stat x x DD f OL x f DS1 V f I V = V V V
stat f OL x f V x R T DS 2
Vx=0 no power used
Vx=5v, Ps = Istat Vdd
Istat = 0.2mA, Ps = 0.2mA x 5v = 1mW
10,000 inverters => 10W V
= 5 V x

32. Figure 3.50 Dynamic current flow in CMOS circuitsV DD V I x D I D V V f f V x
Pd = f CVdd^2
C = 70 fF, f = 100 MHz, Pd = 175uW
10,000 inverters and 20percent switch => 0.35mW
(a) Current flow when input V
(b) Current flow when input V x x
changes from 0 V to 5 V
changes from 5 V to 0 V
Figure Dynamic current flow in CMOS circuits

33. Figure 3.51 Poor use of NMOS and PMOS transistors
VA = VDD – VT
Body effect increases VT to 1.5 VT
VDD=5v VT=1v VOH = 3.5V
Figure Poor use of NMOS and PMOS transistors

34. Figure 3.52 Poor implementation of a CMOS AND gate
Logic
Logic V f
Voltage
value
value V x x V f x 1 2 f 1
1.5 V V 1
1.5 V V DD x 1
1.5 V 2 1 1
3.5 V 1
(a) An AND gate circuit
(b) Truth table and voltage levels
Figure Poor implementation of a CMOS AND gate

35. Figure 3.53 High fan-in NMOS NAND gate
tp = 1.7C / kn’ W/L VDD x k
Figure High fan-in NMOS NAND gate

36. Figure 3.54 High fan-in NMOS NOR gateV DD V f V V V x x x 1 2 k
Figure High fan-in NMOS NOR gate

37. Figure 3.55 The effect of fan-out on propagation delay1 V f f
To inputs of
To inputs of x x n
other inverters n
other inverters C n
(a) Inverter that drives n
other inverters
(b) Equivalent circuit for timing purposes V
for
n = 1 f V DD V
for
n = 4 f
Gnd
Time
(c) Propagation times for different values of n
Figure The effect of fan-out on propagation delay

38. Figure 3.56 A noninverting buffer

39. Figure 3.57 Tri-state buffer
= 0 e x f x f e
= 1 x f
(a) A tri-state buffer
(b) Equivalent circuit e x f e Z 1 Z x f 1 1 1 1
(c) Truth table
(d) Implementation
Figure Tri-state buffer

40. Figure 3.58 Four types of tri-state buffers

41. Figure 3.59 An application of tri-state buffersx f 1 s x 2
Figure An application of tri-state buffers

42. Figure 3.60 A transmission gatex f Z 1 x s
(a) Circuit
(b) Truth table s = x
f = Z s x f s = 1 x
f = x s
(c) Equivalent circuit
(d) Graphical symbol
Figure A transmission gate

43. Figure 3.61 a Exclusive-OR gate= x Å x 1 2 1 2 1 1 x 1 1 1 f = x Å x x 1 2 1 1 2
(a) Truth table
(b) Graphical symbol x 1 x 2 f = x Å x 1 2
(c) Sum-of-products implementation
Figure 3.61 a Exclusive-OR gate

44. Figure 3.61 b CMOS Exclusive-OR gate2 f = x Å x 1 2
(d) CMOS implementation
Figure 3.61 b CMOS Exclusive-OR gate

45. Figure 3.62 A 2-to-1 multiplexer built using transmission gates

46. (a) Dual-inline packageV DD
Gnd
(b) Structure of 7404 chip
Figure A 7400-series chip

47. Figure 3.22 Implementation of f = x1x2 + x2x3V DD
7404
7408
7432 x 1 x 2 x 3 f
Figure Implementation of f = x1x2 + x2x3

48. Figure The buffer chip

49. Figure 3.24 Programmable logic device as a black box
Logic gates
Inputs
and
Outputs
(logic variables)
programmable
(logic functions)
switches
Figure Programmable logic device as a black box

50. Figure 3.25 General structure of a PLAx x x 1 2 n
Input buffers
and
inverters x x x x 1 1 n n P 1
AND plane
OR plane P k f f 1 m
Figure General structure of a PLA

51. Figure 3.63 An example of a NOR-NOR PLA1 2 3
NOR plane V DD V DD V DD S 1 V DD S 2 V DD S 3
NOR plane f f 1 2
Figure An example of a NOR-NOR PLA

52. Figure 3.26 Gate-level diagram of a PLAx x x 1 2 3
Programmable
connections
OR plane P 1 P 2 P 3 P 4
AND plane
Figure Gate-level diagram of a PLA f f 1 2

53. Figure 3.27 Customary schematic of a PLAx x x 1 2 3
OR plane P 1 P 2 P 3 P 4
AND plane f f 1 2
Figure Customary schematic of a PLA

54. (b) A programmable switchx x x 1 2 n V DD = V e S 1 V DD
(b) A programmable switch S 2 V e V DD
++++
+++++ S k
++++ +
++++++
++++ +
(c) EEPROM transistor
(a) Programmable NOR-plane

55. Figure 3.65 A programmable version of a NOR-NOR PLAx x x x 1 2 3 4
NOR plane V DD V DD S 1 S 2 S 3 S 4 S 5 S 6
NOR plane f f
Figure A programmable version of a NOR-NOR PLA 1 2

56. Figure 3.66 A NOR-NOR PLA used for sum-of-productsx x x x 1 2 3 4
NOR plane V DD V DD P 1 P 2 P 3 P 4 P 5 P 6
NOR plane
Figure A NOR-NOR PLA used for sum-of-products f f 1 2

57. Figure 3.28 An example of a PAL1 2 3 P 1 f 1 P 2 P 3 f 2 P 4
AND plane
Figure An example of a PAL

58. Figure 3.67 PAL programmed to implement two functionsx x x x 1 2 3 4 V DD P 1 P 2 f 1 P 3 P 4 P 5 f 2 P 6
NOR plane
Figure PAL programmed to implement two functions

59. Figure 3.29 Output circuitry
Select
Enable f 1
Flip-flop D Q
Clock
To AND plane
Figure Output circuitry

60. Figure 3.30 A PLD programming unit

61. Figure 3.31 A PLCC package with socket

62. Figure 3.32 Structure of a CPLD
I/O block
PAL-like
PAL-like
I/O block
block
block
Interconnection wires
I/O block
PAL-like
PAL-like
I/O block
block
block
Figure Structure of a CPLD

63. Figure 3.33 A section of a CPLD

64. Figure 3.34 CPLD packaging and programming

65. Figure 3.35 Structure of an FPGA
Logic block
Interconnection switches
I/O block
I/O block
I/O block
I/O block
Figure Structure of an FPGA

66. Figure 3.36 A two-input lookup table

67. Figure 3.37 A three-input LUTx 1 x 2
0/1
0/1
0/1
0/1 f
0/1
0/1
0/1
0/1 x 3
Figure A three-input LUT

68. Figure 3.38 Inclusion of a flip-flop with a LUT

69. Figure 3.39 A section of a programmed FPGA

70. Figure 3.68 Pass-transistor switches in FPGAs

71. Figure 3.69 Restoring a high voltage levelDD
SRAM 1 V B V
To logic block A
Figure Restoring a high voltage level

72. Custom Chips Created from scratch.
Designer selects number, placement, and connections for each and every transistor.
Are most dense and highest speed.
Requires a substantial design effort.
Used only when high performance and density is required: processors/memories.

73. Standard-Cell Chips Gates prebuilt and stored in a library.
Gates needed for a design are selected and placed, and wires are routed between them.
Standard-cell chips often called application specific integrated circuits (ASICs).
Saves time since gates are reused.
CAD tools exist to place and route gates.

74. Figure 3.40 A section of two rows in a standard-cell chip

75. Gate-Arrays Parts of chip are prefabricated (transistors).
Parts of chip are custom fabricated (wires).
Provides cost savings since all template wafers are identical.
Many variants exist.

76. Figure 3.41 A sea-of-gates gate array

77. Figure 3.42 An example of a logic function in a gate array

78. Concluding Remarks
Introduced basics of using transistors for digital logic.
Described several types of IC chips:
Standard chips from the 7400 series.
Various types of PLDs.
Custom and semi-custom chips.

79. Figure P3.11 Circuit for problem 3.55V x 1 V x 2 V f
Figure P Circuit for problem 3.55