2. Figure 3.1 Logic values as voltage levels

3. Figure 3.2 NMOS transistor as a switch DrainSource x = "low"x = "high" (a) A simple switch controlled by the inputx V D V S (b) NMOS transistor Gate (c) Simplified symbol for an NMOS transistor V G Substrate (Body)

4. Figure 3.3 PMOS transistor as a switch Gate x = "high"x = "low" (a) A switch with the opposite behavior of Figure 3.2a V G V D V S (b) PMOS transistor (c) Simplified symbol for an PMOS transistor V DD DrainSource Substrate (Body)

5. (a) NMOS transistor V G V D V S = 0 V V S =V DD V D V G Closed switch whenV G =V DD V D = 0 V Open switch whenV G = 0 V V D Open switch whenV G =V DD V D V Closed switch whenV G = 0 V V D =V DD V (b) PMOS transistor Figure 3.4 NMOS and PMOS transistors in logic circuits

6. (b) Simplified circuit diagram V x V f V DD xf (c) Graphical symbols xf R V x V f R + - (a) Circuit diagram 5 V Figure 3.5 A NOT gate built using NMOS technology

7. Figure 3.6 NMOS realization of a NAND gate V f V DD (a) Circuit (c) Graphical symbols (b) Truth table ff 0 0 1 1 0 1 0 1 1 1 1 0 x 1 x 2 f V x 2 V x 1 x 1 x 2 x 1 x 2

8. Figure 3.7 NMOS realization of a NOR gate

9. Figure 3.8 NMOS realization of an AND gate (a) Circuit (c) Graphical symbols (b) Truth table f f 0 0 1 1 0 1 0 1 0 0 0 1 x 1 x 2 f V f V DD A V x 1 V x 2 x 1 x 2 x 1 x 2 V

10. Figure 3.9 NMOS realization of an OR gate

11. Figure 3.10 Structure of an NMOS circuit

12. Figure 3.11 Structure of a CMOS circuit

13. Figure 3.12 CMOS realization of a NOT gate (a) Circuit V f V DD V x (b) Truth table and transistor states on off on 1 0 0 1 fx T 1 T 2 T 1 T 2

14. Figure 3.13 CMOS realization of a NAND gate

15. Figure 3.14 CMOS realization of a NOR gate

16. Figure 3.15 CMOS realization of an AND gate

17. Figure 3.16 A CMOS complex gate

18. Figure 3.17 A CMOS complex gate

19. Figure 3.18 Voltage levels in a CMOS circuit

20. Figure 3.19 Interpretation of voltage levels (b) Positive logic truth table and gate symbol f 0 0 1 1 0 1 0 1 1 1 1 0 x 1 x 2 f x 1 x 2 (c) Negative logic truth table and gate symbol 1 1 0 0 1 0 1 0 0 0 0 1 x 1 x 2 f f x 1 x 2 (a) Voltage levels L H L L H H L H H H H L V x 1 V x 2 V f

21. Figure 3.20 Interpretation of voltage levels (b) Positive logic f 0 0 1 1 0 1 0 1 0 0 0 1 x 1 x 2 f x 1 x 2 (c) Negative logic 1 1 0 0 1 0 1 0 1 1 1 0 x 1 x 2 f f x 1 x 2 (a) Voltage levels L H L L H H L H L L L H V x 1 V x 2 V f

22. Figure 3.21 A 7400-series chip (a) Dual-inline package (b) Structure of 7404 chip V DD Gnd

23. Figure 3.22 Implementation of f = x 1 x 2 + x 2 x 3 V DD x 1 x 2 x 3 f 7404 74087432

24. Figure 3.23 The 74244 buffer chip

25. Figure 3.24 Programmable logic device as a black box Logic gates and programmable switches Inputs (logic variables) Outputs (logic functions)

26. Figure 3.25 General structure of a PLA f 1 AND plane OR plane Input buffers inverters and P 1 P k f m x 1 x 2 x n x 1 x 1 x n x n

27. Figure 3.26 Gate-level diagram of a PLA f 1 P 1 P 2 f 2 x 1 x 2 x 3 OR plane Programmable AND plane connections P 3 P 4

28. Figure 3.27 Customary schematic of a PLA f 1 P 1 P 2 f 2 x 1 x 2 x 3 OR plane AND plane P 3 P 4

29. Figure 3.28 An example of a PLA f 1 P 1 P 2 f 2 x 1 x 2 x 3 AND plane P 3 P 4

30. Figure 3.29 Output circuitry f 1 To AND plane DQ Clock Select Enable Flip-flop

31. Figure 3.30 A PLD programming unit

32. Figure 3.31 A PLCC package with socket

33. Figure 3.32 Structure of a CPLD PAL-like block I/O block PAL-like block I/O block PAL-like block I/O block PAL-like block I/O block Interconnection wires

34. Figure 3.33 A section of a CPLD

35. Figure 3.34 CPLD packaging and programming

36. Figure 3.35 Structure of an FPGA Logic block Interconnection switches I/O block

37. Figure 3.36 A two-input lookup table

38. Figure 3.37 A three-input LUT f 0/1 x 2 x 3 x 1

39. Figure 3.38 Inclusion of a flip-flop with a LUT

40. Figure 3.39 A section of a programmed FPGA

41. Figure 3.40 A section of two rows in a standard-cell chip

42. Figure 3.41 A sea-of-gates gate array

43. Figure 3.42 An example of a logic function in a gate array

44. Figure 3.43 a NMOS transistor when turned off +++++++++++++++++++++++++ +++++++++ +++++++++++ Drain (type n) Source (type n) Substrate (type p) SiO 2 (a) WhenV GS = 0 V, the transistor is off V S 0V= V G 0V= V D ++++++

45. +++++++++++++ +++++++++++++++++++ ++++++++++++++++++++++++++++ Channel (type n) SiO 2 V DD (b) WhenV GS = 5 V, the transistor is on +++++++++ V D 0V= V G 5V= V S 0V= Figure 3.43 b NMOS transistor when turned on

46. Figure 3.44 Current-voltage relationship in the NMOS transistor I D 0 Triode V DS Saturation V GS V T –

47. Figure 3.45 Voltage levels in the NMOS inverter V DD (b) V x = 5 V I stat R R DS V f V OL = (a) NMOS NOT gate V f V DD V x

48. Figure 3.46 Voltage transfer characteristics for the CMOS inverter V f V x V OL 0V= V OH V DD = V T V IL V IH V DD V T –  V V 2 — Slope1–=

49. Figure 3.47 Parasitic capacitance in integrated circuits

50. Figure 3.48 Voltage waveforms for logic gates

51. Figure 3.49 Transistor sizes

52. Figure 3.50 Dynamic current flow in CMOS circuits V DD V f V x I D V x V f I D (a) Current flow when input V x changes from 0 V to 5 V (b) Current flow when input V x changes from 5 V to 0 V

53. Figure 3.51 Poor use of NMOS and PMOS transistors

54. Figure 3.52 Poor implementation of a CMOS AND gate (a) An AND gate circuit V f V DD (b) Truth table and voltage levels 1.5 V 0 1 0 0 1 1 0 1 3.5 V f 0 0 0 1 V x 1 V x 2 x 1 x 2 V f Voltage Logic value Logic value

55. Figure 3.53 High fan-in NMOS NAND gate

56. Figure 3.54 High fan-in NMOS NOR gate x k V f V DD V x 1 V x 2 V

57. Figure 3.55 The effect of fan-out on propagation delay (b) Equivalent circuit for timing purposes x f (a) Inverter that drivesn other inverters To inputs of n other inverters To inputs of n other inverters C n x V f forn =1V f forn =4V f V DD Gnd Time0 (c) Propagation times for different values ofn N 1

58. Figure 3.56 A noninverting buffer

59. Figure 3.57 Tri-state buffer (b) Equivalent circuit (c) Truth table x f e (a) A tri-state buffer 0 0 1 1 0 1 0 1 Z Z 0 1 f ex x f e = 0 e = 1 x f f x e (d) Implementation

60. Figure 3.58 Four types of tri-state buffers

61. Figure 3.59 An application of tri-state buffers f x 1 x 2 s

62. Figure 3.60 A transmission gate (a) Circuit fx (b) Truth table Z x 0 1 fs s s s0= s1= x x f = Z f = x (c) Equivalent circuit(d) Graphical symbol f x s s

63. Figure 3.61 a Exclusive-OR gate (b) Graphical symbol(a) Truth table 0 0 1 1 0 1 0 1 0 1 1 0 x 1 x 2 x 1 x 2 fx 1 x 2  = fx 1 x 2  = (c) Sum-of-products implementation fx 1 x 2  = x 1 x 2

64. (d) CMOS implementation x 1 x 2 fx 1 x 2  = Figure 3.61 b CMOS Exclusive-OR gate

65. Figure 3.62 A 2-to-1 multiplexer built using transmission gates x 1 x 2 f s

66. Figure 3.63 An example of a NOR-NOR PLA V DD V V V V S 1 S 2 S 3 NOR plane f 1 f 2 x 1 x 2 x 3

67. V DD V V S 1 S 2 S k x 1 x 2 x n (a) Programmable NOR-plane = V e (b) A programmable switch V e ++++ +++++ +++++++++++ + (c) EEPROM transistor Figure 3.64 A programmable NOR plane

68. Figure 3.65 A programmable version of a NOR-NOR PLA f 1 S 1 S 2 f 2 x 1 x 2 x 3 NOR plane S 3 S 4 x 4 S 5 S 6 V DD V

69. Figure 3.66 A NOR-NOR PLA used for sum-of-products f 1 P 1 P 2 f 2 x 1 x 2 x 3 NOR plane P 3 P 4 x 4 P 5 P 6 V DD V

70. Figure 3.67 PAL programmed to implement two functions f 2 P 1 P 2 x 1 x 2 x 3 NOR plane P 3 P 4 x 4 P 5 P 6 V DD f 1

71. Figure 3.68 Pass-transistor switches in FPGAs

72. Figure 3.69 Restoring a high voltage level V DD To logic block 1 SRAM V A V B

73. Figure P3.1 A sum-of-products CMOS circuit

74. Figure P3.2 A CMOS circuit built with multiplexers x 1 x 2 x 3 g

75. Figure P3.3 Circuit for problem 3.3 h x 1 x 2 A x 3

76. Figure P3.4 A three-input CMOS circuit

77. Figure P3.5 A four-input CMOS circuit

78. Figure P3.6 The pull-down network in a CMOS circuit V x 1 V x 2 V x 3 V f

79. Figure P3.7 The pull-up network in a CMOS circuit

80. Figure P3.8 The pseudo-NMOS inverter V f V DD V x

81. Figure P3.9 A gate-array logic cell out in1 2 3 4 5 6 7

82. Figure P3.10 Circuit for problem 3.54

83. Figure P3.11 Circuit for problem 3.55 V f V x 1 V x 2