1. “DIRAC-PHASE-1” – Construction stage 1 at the international Facility for Antiproton and Ion Research (FAIR) at GSI, Darmstadt Task 8 - HADES1 Resistive Plate Chamber (RPC) Time of Flight Wall P.Fonte LIP-Coimbra Construction of a high-granularity and large area time of flight wall for the HADES spectrometer based on Resistive Plate Counters technology. Production of fast, wide-band, analog electronic and multi-hit digital electronic with the aim to achieve time resolution better than 100 ps and feasible to run in a high multiplicity environment of heavy ion collisions. 2 nd Annual Report meeting GSI, 11-10-2007

2. DIRAC-PHASE-1 TASK 8 – HADES1: Resistive Plate Chamber TOF WallP.Fonte 2 nd Annual Report meeting 11-10-2007 Participants & Tasks InstituteTaskPeople GSI Gesellschaft für Schwerionenforschung mbH Darmstadt, Germany Electronics production. General coordination. D. Gonzalez, W. Koenig, M.Traxler INR Institute for Nuclear Research Russian Academy of Science Moscow, Russia Particle identification software. F. Guber JU M. Smoluchowski Institute of Physics Jagiellonian University Kraków, Poland Digital time-measurement electronics. M. Kajetanowicz, K. Korcyl, W. Krzemien, M. Palka, P. Salabura, R. Trebacz LIP- Coimbra Laboratório de Instrumentação e Física Experimental de Partículas Coimbra, Portugal RPC detectors and gas enclosures. Task coordination. A.Blanco, L.Lopes, N.Carolino, A.Pereira, P.Fonte, C.Silva, O.Orlando USC Departamento de Física de Partículas, University of Santiago de Compostela, Compostela, Spain Analog front-end electronics. Detector software. D. Belver, P.Cabanelas, E. Castro, J.A. Garzon, M.Zapata (Techn) Along with an important contribution of CSIC, Valencia: A.Gil.

3. DIRAC-PHASE-1 TASK 8 – HADES1: Resistive Plate Chamber TOF WallP.Fonte 2 nd Annual Report meeting 11-10-2007 Workplan status Read-out board design freeze- out 2 full chambers produced Full system test FEE design freeze-out 6 full chambers produced Today Beamtime next week 200620072008

4. DIRAC-PHASE-1 TASK 8 – HADES1: Resistive Plate Chamber TOF WallP.Fonte 2 nd Annual Report meeting 11-10-2007 Detectors (prototype sextant) LIP

5. DIRAC-PHASE-1 TASK 8 – HADES1: Resistive Plate Chamber TOF WallP.Fonte 2 nd Annual Report meeting 11-10-2007 Detectors (prototype sextant) LIP

6. DIRAC-PHASE-1 TASK 8 – HADES1: Resistive Plate Chamber TOF WallP.Fonte 2 nd Annual Report meeting 11-10-2007 Detectors (prototype sextant) Crosstalk on the 1-2 mV/V level at 300MHz LIP

7. DIRAC-PHASE-1 TASK 8 – HADES1: Resistive Plate Chamber TOF WallP.Fonte 2 nd Annual Report meeting 11-10-2007 Detectors (prototype sextant) LIP

8. DIRAC-PHASE-1 TASK 8 – HADES1: Resistive Plate Chamber TOF WallP.Fonte 2 nd Annual Report meeting 11-10-2007 Detectors (prototype sextant) LIP

9. DIRAC-PHASE-1 TASK 8 – HADES1: Resistive Plate Chamber TOF WallP.Fonte 2 nd Annual Report meeting 11-10-2007 Motherboard (MB) + Daughterboard (DB) philosophy. DB Step5 (4 channels): 1) Amplifier stage → Ph-BGM1013 + Q-ToT stage with TI OPA690. 2) Discriminator stage: - Dual MAX 9601 discriminator. One discriminator/channel. - PECL-LVDS TI SN65LVDS100 converter. - BFT92 transistor for multiplicity trigger sum. 3) Output: 40-pin SAMTEC HSEC8 connector MB (32 channels) by CSIC Valencia : - Provides regulated Voltage, DAC thresholds, test pulses, output path to DAQ… 4 ch. out C ToT Integrator Amplifier Step PECL- LVDS ToF-Threshold In OPA690 Wideband Op. Amplifier BGM1013 (35dB, 2GHz) MAX9601-2ch 500ps Propagation Delay SN65LVDS100 C Latch enable/ R 2k2 Trigger Out. Σ 4ch. BFT92 Wideband PNP Transistor Discriminator Step Q Q/ R C 2nd integration RC=20ns Task: FEE design USC, GSI, U.Valencia: ESTRELA FEE Frozen in February 2007

10. DIRAC-PHASE-1 TASK 8 – HADES1: Resistive Plate Chamber TOF WallP.Fonte 2 nd Annual Report meeting 11-10-2007 Motherboards Daugtherboards provided (+ power supplies) by CSIC,Valencia (not in this project) Task: FEE prototype USC, GSI, U.Valencia: ESTRELA FEE

11. DIRAC-PHASE-1 TASK 8 – HADES1: Resistive Plate Chamber TOF WallP.Fonte 2 nd Annual Report meeting 11-10-2007 Task: FEE prototype USC, GSI, U.Valencia: ESTRELA FEE

12. DIRAC-PHASE-1 TASK 8 – HADES1: Resistive Plate Chamber TOF WallP.Fonte 2 nd Annual Report meeting 11-10-2007 Task: FEE prototype status USC, GSI, U.Valencia: ESTRELA FEE - DBs 108 DBs boards manufactured 95 of them has been loaded and tested: 83 with 4ch working 8 with only 3 ch working 3 with only 2 ch working 1 has a shortcut - MBs 15 MBs manufactured, 12 MB loaded, tested and working 3 MBs lack components: 1 MB with one resistor missing 2 MB with some capacitor missing 5 miniMBs manufactured 4 loaded and working properly Summary: All MBs and miniMBs mounted on the detector with 362channels (=181cells) working 50ch (=25cells) not instrumented (around 12%)

13. DIRAC-PHASE-1 TASK 8 – HADES1: Resistive Plate Chamber TOF WallP.Fonte 2 nd Annual Report meeting 11-10-2007 Task: Software USC Slow control - Thresholds DACs controlled individually, from a PC, via SPI protocol - Measurement of the temperatures sensors at the TRB is ready - Slow control to be implemented in EPICS not ready Detector software Almost all the decoding and calibration basic programs are already written and implemented in the HADES standard analysis framework Hydra. - Lookup table: sector/column/cell/side DAQ channels and FEE address - Decoding/Calibration chain from raw data to hit level (including diagnostic and monitoring histograms) - Programs correlating RPC hits with MDCs and Shower hits for efficiencies analysis - Macros for the analysis of time and position resolution and FEE performances - Simulation of C-Be collisions at the hit level in order to compare the results with the expected distributions.

14. DIRAC-PHASE-1 TASK 8 – HADES1: Resistive Plate Chamber TOF WallP.Fonte 2 nd Annual Report meeting 11-10-2007 Task: Readout board production TRB Features: ➢ Four HPTDC each 32 channels => 128 channels ➢ Single chip computer with 100MBit/s Ethernet ➢ FPGA as board controller ➢ DC/DC 48V ➢ Buffer Memory Status: In production ➢ The board was fully integrated with HADES DAQ environment ➢ Was used for readout in Nov 2005, May 2006 and April-May 2007 beam times ➢ It is running stably with up to 80kHz LVL1 (for small events) and 20 kHz LVL2 rate, ➢ data rate to 1.2 MB/s 12/24 units have been produced JU, GSI

15. DIRAC-PHASE-1 TASK 8 – HADES1: Resistive Plate Chamber TOF WallP.Fonte 2 nd Annual Report meeting 11-10-2007 Major difficulties (mechanics) HV distribution Full redesign: epoxy isolation (unreliable)  seamless acrylic box Mechanical drawing Needed to learn new CAD tool  perfect prototype

16. DIRAC-PHASE-1 TASK 8 – HADES1: Resistive Plate Chamber TOF WallP.Fonte 2 nd Annual Report meeting 11-10-2007 Major difficulties (electronics) Design GHz-bandwidth dense mixed-signal circuit – not easy (frozen February 2007) Production Component ordering difficulties Loading went not so well – lots of rework needed HADES April-May beam time got on the way

17. DIRAC-PHASE-1 TASK 8 – HADES1: Resistive Plate Chamber TOF WallP.Fonte 2 nd Annual Report meeting 11-10-2007 M3: Full system prototype Full-system prototype 400 time+charge channels Beamtime next week

18. DIRAC-PHASE-1 TASK 8 – HADES1: Resistive Plate Chamber TOF WallP.Fonte 2 nd Annual Report meeting 11-10-2007 Workplan update M32M33M34M35M36M37M38M39M40M41M42M43M44M45M46M47M48 2009 SIS shutdown    