1. copyright 2002 An Analog Turbo Decoder for an (8,4) Product Code Matthew C. Valenti Assistant Professor Lane Dept. of Comp. Sci. & Elect. Eng. West Virginia University Morgantown, WV mvalenti@wvu.edu Neiyer Correal and Joe Heck Florida Communications Research Labs Motorola Plantation, FL

2. © 2002 Motivation & Goals Motivation  Iteratively decodable code are capable of near- Shannon limit performance. e.g. turbo codes, LDPC codes, turbo product codes.  Digital hardware has its limitations Clock functions demand power and real estate. Turbo decoding uses nonlinear functions that are awkward in digital but natural in analog. Goal of this study  To design and implement a simple iterative decoder in analog. Simple: (8,4) product code created using a 2 by 2 array of (3,2) single parity check codes.  Target throughput is 1 Gbps

3. © 2002 Overview of Talk Related work Single parity check (SPC) codes  Encoder  Soft-input/Soft-output (SISO) decoder  Analog design of the SISO decoder Turbo product codes  Encoder  Turbo Decoder Comments & Conclusions

4. © 2002 Related Work Inspiration: Carver Mead (Cal Tech) 1980’s  Observation: nervous cells and CMOS transistors operating in subthreshold mode have same physics.  Adaptive analog systems with the robustness of digital yet 2-orders of magnitude reduction in power.  Primarily image processing applications. Recent work: Turbo Decoding  J. Hagenauer (T.U. Munich) Log-likelihood domain circuits.  Loeliger + Lustenberger (E.T.H. Zurich) Circuits operate on raw probabilities rather than LLRs.

5. © 2002 Single Parity Check Codes Generic (n,k) SPC code:  The input to the SPC encoder is a stream of k data bits: {u 1, u 2, …, u k }  A single parity bit is created by xor-ing the data: u p = u 1  u 2  u k  The n=k+1 bit output is the k input bits and the parity bit: u = {u 1, u 2, …, u k,u p } The (3,2) SPC code:  Let the two input bits be denoted u j and u k  The parity bit is u j,k = u j  u k  The output is u = {u j, u k, u j,k }

6. © 2002 Modulation and Channel Model BPSK modulation  x = +1 if u = 0 and x = -1 if u = 1  Modulated code word: x = {x j, x k, x j,k }  Received code word: y = {y j, y k, y j,k } Channel  characterized by conditional pdf: f(y|x) AWGN: Rayleigh flat-fading

7. © 2002 Scaling the Input Input to the SISO decoder must be scaled:  In log-likelihood form:  Decoder input is: r={r j,r k,r j,k }={L(y j |x j ),L(y k |x k ),L(y j,k |x j,k )} SNR fade coefficient (=1 for AWGN)

8. © 2002 APP SISO Decoder Input-output relationships (BCRJ algorithm): SISO dec. #1 rkrk rjrj r j,k scaled channel observations L(x k ) L(x j ) a priori information from other decoders L e (x j ) L e (x k ) extrinsic information to other decoders L(u j |y) L(u k |y) a posteriori estimates: used to make final bit decision extrinsic information: exploits structure of code a posteriori LLR estimates

9. © 2002 Box-Plus Operator The heart of the decoder is a soft-xor operation, also called “box-plus” This can be implemented in analog by a modified Gilbert multiplier

10. © 2002 Current Mirror Current Mirror Modified Gilbert Multiplier

11. Computing Extrinsic Information V gp r k /V T L(x k )/V T V dda V bn r j,k /V T L e (x j )/V T Q 10 Q 13 R 12 Q0Q0 Q1Q1 L(x k ) L e (x j ) rkrk r j,k 50  A + + + +

12. Computing a Posteriori LLR + r j /V T V dda + L(x j )/V T + L e (x j )/V T R8R8 R6R6 R7R7 V bn L(x j |y)/V T + L(x j |y) rjrj L(x j ) L e (x j )

13. © 2002 SISO Decoder for (3,2) SPC Code Components:  2 units for computing extrinsic information. 6 PMOS + 10 BJT transistors + 7 resistors each.  2 units for computing a priori LLR. 9 BJT transistors + 9 resistors each. L(x j ) L(x k ) L e (x j ) L e (x k ) rjrj rkrk L(x j |y) r j,k L(x k |y)

14. © 2002 Product Codes A more powerful code can be created by using multiple SPC codes.  2 by 2 array of SPC codes can correct a single error when using hard decision decoding.  However, we want a soft-decision decoder. == u1u1 u2u2 u 1,2 u3u3 u4u4 u 3,4 u 1,3 u 2,4

15. © 2002 Turbo Decoding of Product Codes r1r1 r2r2 r 1,2 r3r3 r4r4 r 3,4 r 1,3 r 2,4 L e (x 1 )L e (x 2 )L e (x 3 )L e (x 4 ) L e (x 1 ) L e (x 3 ) L e (x 2 ) L e (x 4 )

16. © 2002 Turbo Decoder L(u 1 |y) L(u 2 |y) L(u 3 |y) L(u 4 |y) horiz. dec. #1 horiz. dec. #2 vertical dec. #1 vertical dec. #2 r1r1 r2r2 r 1,2 r 3,4 r3r3 r4r4 r 1,3 r 2,4

17. © 2002 Vertical Decoder The a priori LLR is computed using the output of the horizontal decoding. Thus, the vertical decoder does not need the three-input adders L(x j ) L(x k ) L e (x j ) L e (x k ) rjrj rkrk r j,k

18. © 2002 Circuit Complexity Two horizontal decoders, each with:  2 units for computing extrinsic information.  2 units for computing a priori LLR. Two vertical decoders, each with:  2 units for computing extrinsic information. Total complexity:  8 units for computing extrinsic information.  4 units for computing a priori LLR.  48 PMOS transistors  116 BJT transistors  92 Resistors

19. © 2002 Comments on Analog Decoding Complicated codes can be decoded using the same approach.  Cascade of analog cells. Problems  Transistor mismatch. Equivalent to having additional noise at input. Current transistor tolerances have same impact as using 5-10 bit quantization in a digital implementation.  Thermal gradients Proper scaling will mitigate intercell gradients. However, intracell gradients will hurt performance.  Decoding serial data in parallel Need to store analog values (e.g. sample/hold). Could work well with multicarrier modulation.  Design and test Spice-level simulations needed, but take too long.

20. © 2002 Conclusion Advantages of analog decoders:  No costly clock functions  smaller footprint/expense.  No concept of iteration  faster convergence.  easily implemented nonlinear functions. Implementation issues may hinder performance  However, suboptimality in local cells is okay as long as overall system performance is acceptable. Extensions of this work  (n,k) SPC code for k>2.  Product code with 3 dimensions or more.  Other types of codes: Hamming, BCH.  Turbo and LDPC codes.  Other iterative processing schemes, e.g. turbo-EQ