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© 2009, Renesas Technology America, Inc., All Rights Reserved 1 Course Introduction  Purpose This course provides an introduction to the peripheral functions.

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Presentation on theme: "© 2009, Renesas Technology America, Inc., All Rights Reserved 1 Course Introduction  Purpose This course provides an introduction to the peripheral functions."— Presentation transcript:

1 © 2009, Renesas Technology America, Inc., All Rights Reserved 1 Course Introduction  Purpose This course provides an introduction to the peripheral functions built into R8C Tiny series microcontrollers (MCUs).  Objective  Learn about the features and operation of the TimerRA, TimerRB, TimerRC, TimerRD and TimerRE functions.  Understand the basics of the Watchdog Timer.  Discover how the Power-on Reset (POR) and Low-Voltage Detect (LVD) functions operate.  Content  33 pages  5 questions  Learning Time  35 minutes

2 © 2009, Renesas Technology America, Inc., All Rights Reserved 2 Versatile Set of Timers The Watchdog Timer is covered separately in this course.

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4 © 2009, Renesas Technology America, Inc., All Rights Reserved 4 Timer RA

5 © 2009, Renesas Technology America, Inc., All Rights Reserved 5 Timer RB

6 © 2009, Renesas Technology America, Inc., All Rights Reserved 6 Timer RC

7 © 2009, Renesas Technology America, Inc., All Rights Reserved 7 Timer RD

8 © 2009, Renesas Technology America, Inc., All Rights Reserved 8 Timer RE

9 © 2009, Renesas Technology America, Inc., All Rights Reserved 9 FF Timer Mode FF Reload register FF 2 1 0 Count Start flag TRAPRE Pre-scalerTRA Counter Timer RA Interrupt f2 fOCO f8 f1 Count Source The timer counts an internally generated count source.  Operation:When the timer underflows, it reloads the register contents before continuing to count. 1 0 1 10012 00h Timer RA Mode register Timer RA Mode Register is used to put Timer RA into the Timer Mode and start/stop the counting. 08h 0 12 Example: Timer RA

10 © 2009, Renesas Technology America, Inc., All Rights Reserved 10 Pulse Output Mode 1 Reload register 2 2 0 Count Start flag TRAPRE Pre-scalerTRA Counter f2 fOCO f8 f1 Count Source 1 Toggle flip-flop Q Q CK 01 TMOD bits The timer counts an internally generated count source, the TRAO pin outputs a pulse whose polarity is inverted when the timer underflows.  Operation:When the timer underflows, it reloads the register contents before continuing to count. TRAO 1 Example: Timer RA

11 © 2009, Renesas Technology America, Inc., All Rights Reserved 11 Pulse Output Mode: Timer RA Example 1 Reload Register 2 2 0 Count Start Flag PREX registerTX register f2 fOCO f8 f1 Count Source 1 Toggle flip-flop Q Q CK 01 TMOD bits The timer counts an internally generated count source, the TRAO pin outputs a pulse whose polarity is inverted when the timer underflows.  Operation:When the timer underflows, it reloads the register contents before continuing to count. CNTR0 1

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13 © 2009, Renesas Technology America, Inc., All Rights Reserved 13 Generate Complementary Outputs 1 Reload register 2 2 0 Count Start flag TRAPRE Pre-scalerTRA Counter f2 fOCO f8 f1 Count Source 1 Toggle flip-flop Q Q CK 01 TMOD bits 1 TRAIO TRAO TRAIO has the option to be a port pin or an inverted output of TRAO 1 Example: Timer RA

14 © 2009, Renesas Technology America, Inc., All Rights Reserved 14 Event Counter Mode FF Reload register FF 0 Count Start Flag TRAPRE Pre-scalerTRA Counter External Count Source 1 TRAIO Timer RA Mode register 00h02h 0 0 2 2 0Ah 102 Timer RA Interrupt Example: Timer RA The timer counts an external signal fed to TRAIO pin.  Operation: When the timer underflows, it reloads the register contents before continuing to count. Timer RA Mode Register is use to put Timer RA into Event Counter Mode, selects the active edge of the count Source, and starts/stops the counter.

15 © 2009, Renesas Technology America, Inc., All Rights Reserved 15 Pulse Width Measurement Mode 0 Reload register 5 5 0 0 Count Start flag TRAPRE Pre-scalerTRA Counter f2 f32 f8 f1 1 TRAIO Timer RA Interrupt TRAIO pin IR bit in TRAIC register Count Stop The timer measures the pulse width of an external signal fed into the TRAIO pin. TUNDF bit in TRACR register Timer Underflow Count Source Example: Timer RA

16 © 2009, Renesas Technology America, Inc., All Rights Reserved 16 Pulse Period Measurement Mode: Timer RA TRAIO pin Underflow signal of prescaler TRA contents 0F0E0D0F0E0D0C0B0A090F0E 0F0E0D Timer RA interrupt Timer RA active Edge detected ( TEGDF bit) 0B0A 09 000F 000F Timer RA underflow (TUNDF bit) Contents of read out buffer Timer RA reloads Timer RA read Cleared to “0” by program Period being measured Timer RA reloads

17 © 2009, Renesas Technology America, Inc., All Rights Reserved 17 Programmable Waveform Gen. Mode FF Reload registerTRBSC register FF 1 0 Count Start flag TRBPRE Pre-scalerTimer RB Counter f2 TRA UNF f8 f1 Count Source 1 Toggle flip-flop Q Q CK 01 TMOD bits FF TRBPR register TRBO P3_1 bit 021010210FF Primary period Secondary period A signal is output from the TRBO pin which is inverted each time the counter underflows, it reloads the contents of primary reload register and secondary reload register alternately before continuing to count. 0 0 21 102101 Example: Timer RB

18 © 2009, Renesas Technology America, Inc., All Rights Reserved 18 Programmable One-Shot Gen. Mode 0 Reload register 1 1 0 0 Count Start flag TRBPRE Pre-scalerTimer RB Counter f2 TRA UDF f8 f1 Count Source 1 Toggle flip-flop Q Q CK 01 TMOD bits TRBPR register TRBO P3_2 bit 0210102101 Digital Filter Input polarity selected to be one edge or both edges Polarity select TSTART TOSSTF TMODx INT0ENINT0PL INT0 Example: Timer RB

19 © 2009, Renesas Technology America, Inc., All Rights Reserved 19 Generating a Precise Pulse Width 010001 Contents of TRA TSTART bit in TRACR register Output of TRAO out pin Pre-scaler RA underflow signal Count Source IR bit in TRAIC register Count Starts Waveform Output Starts Waveform Output ends Timer RA primary reloads Set to “1” by program Set to “0” by program

20 © 2009, Renesas Technology America, Inc., All Rights Reserved 20 Programmable Wait One Shot Generation Mode: Timer RB In this mode, upon program or external trigger input, the device outputs the one-shot pulse from the TRBO pin after waiting for a given length of time. When a trigger occurs, the timer starts outputting a pulse for a given length of time equal to the set value in the TRBSC register. This is only after waiting for the TRBPR register to overflow. 010002 Count Source Timer RB One Shot bit Contents of TRBPR Prescaler RB underflow signal Interrupt Request bit in Timer RB Interrupt Control register TRBO out pin 010001 Set to “1” by program, or set to “1” by INT0 pin input trigger Set to “0” when counting completed Count Starts Timer RB secondary reloads Timer RB primary reloads Waveform output starts Waveform output end Wait starts

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22 © 2009, Renesas Technology America, Inc., All Rights Reserved 22 Input Capture Mode

23 © 2009, Renesas Technology America, Inc., All Rights Reserved 23 TimerRC Timer Mode Output Compare

24 © 2009, Renesas Technology America, Inc., All Rights Reserved 24 TimerRC PWM Mode

25 © 2009, Renesas Technology America, Inc., All Rights Reserved 25 TimerRD Complementary PWM Mode

26 © 2009, Renesas Technology America, Inc., All Rights Reserved 26 TimerRD Complementary PWM Mode

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28 © 2009, Renesas Technology America, Inc., All Rights Reserved 28 Watchdog Timer 1/16 1/128 Watchdog Timer Interrupt Request Watchdog Timer Reset PM12 = 0 PM12 = 1 WDC7 = 0 WDC7 = 1 Set to 7FFF 16 Write to WDTS register RESET CPU Clock Pre-scaler Watchdog Timer The WDT circuit contains a 15-bit counter that counts down the clock derived by dividing the CPU clock by 16 or 128 using the pre-scaler.

29 © 2009, Renesas Technology America, Inc., All Rights Reserved 29 Power-On Reset Function CPU Res et IC CPU Res et IC Reset CCT No External Reset IC required 0.5 Vdet 5.0 time Internal state in Reset CPU ResetReset Released (1/f(RING)) X 32 Vdet = 3.8V ± 0.5V More Than 1ms VCC [V] S R Q 5-bit counter Internal RESET signal RESET fRING-S VCC > Vdet detection trigger 5KΩ

30 © 2009, Renesas Technology America, Inc., All Rights Reserved 30 Low Voltage Detect Function 2.7 Vdet 5.0 time Internal state in Reset CPU Reset Reset Released (1/f(RING)) X 32 Vdet = 3.8V ± 0.5V VCC [V] Reset Released The operation of the LVD function is essentially the same as the operation of the POR.

31 © 2009, Renesas Technology America, Inc., All Rights Reserved 31 LVD Operation Voltage Detect Enable 5.0 V Vdet Sampling time 3 to 4 clocks (1/f(RING)) X 32 Internal Reset Signal Voltage Detect Flag Voltage Detect Interrupt Request Sampling time 3 to 4 clocks VCC Interrupt Acknowledge 5.0 V

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33 © 2009, Renesas Technology America, Inc., All Rights Reserved 33  Timer functions  Timer modes  Watchdog timer  Power-On Reset function  Low Voltage Detect function Course Summary http://www.renesasinteractive.com

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