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ECE 447: Lecture 8 Timer System (1). ECE 447: 68HC11 Timer System 1.Generating delays - imposing a specific delay between two points in the program by.

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Presentation on theme: "ECE 447: Lecture 8 Timer System (1). ECE 447: 68HC11 Timer System 1.Generating delays - imposing a specific delay between two points in the program by."— Presentation transcript:

1 ECE 447: Lecture 8 Timer System (1)

2 ECE 447: 68HC11 Timer System 1.Generating delays - imposing a specific delay between two points in the program by polling. label 1 label2 instr1 instr2 instrN delay 2. Pulse accumulation - counting the number of pulses

3 ECE 447: 68HC11 Timer System 3. Input capture - measuring the time between signal edges 4. Output compare - generating signals with the given timing characteristics start stop startstop pulse width single pulseperiodical signal period

4 ECE 447: 68HC11 Timer System 5. Real Time Interrupt – Produce a period signal for the 68HC11. period The Real Time Interrupt will allow a piece of code to be executed at a given period. This can be used to implement a Real-Time clock.

5 ECE447: Timer I/O Pins PA0 - Input Capture 3 (IC3) PA1 -Input Capture 2 (IC2) PA2 - Input Capture 1 (IC1) PA3 - Input Capture 4/ Output compare 5 (IC4/OC5) PA4 - Output Compare 4 (OC4) PA5 - Output Compare 3 (OC3) PA6 - Output Compare 2 (OC2) PA7 - Pulse Accumulator Input (PAI)

6 ECE 447: Setting and Clearing Event Flags Example for Input Capture 1 Unusual procedure!!! Set a flagClear a flag #define IC1F 0x04 TFLG1 = IC1F; Cannot be done in software!!! Set by a preselected edge at the PA2 input Cleared by writing 1 to the corresponding bit location!!!

7 ECE447: Measuring Pulse Widths Timer overflows 100  s < width < 32.768 ms width  100  s width  32.768 ms start stop start stop start stop

8 ECE 447: Measuring intervals <2 16 clock cycles start 0 FFFF stop

9 ECE 447: Measuring intervals <2 16 clock cycles (overflow) start 0 FFFF 12 stop

10 ECE 447: Measuring intervals >2 16 clock cycles start stop 0 FFFF 12 N=3 R

11 ECE 447: Measuring intervals >2 16 clock cycles start stop 0 FFFF 12 3 R2 R1 N=4 R1+R2=R


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