1. Interrupts general concepts interrupt systems

2. Interrupts - concepts 2/27 Interrupt - the event inside or outside of microprocessor system, requested immediate service by software executed by microprocessor.

3. Interrupts - concepts 3/27 Interrupt service routine - instruction sequence realising action required by interrupt. reading inputs calculations writing outputs open valve

4. Interrupts - concepts 4/27 Main program (background program) - program executed by processor during the absence of interrupts ATTENTION: operation of interrupted program can’t be disturbed by interrupt service... A:=200 B:=44 A:=A+B M[201]:=A... in main program:... B:=11 A:=B*B M[101]:=A... in interrupt service routine: M[201]=132 M[101]=121... A:=200 B:=44 A:=A+B M[201]:=A... in main program : A,B  stack... B:=11 A:=B*B M[101]:=A... stack  B,A in interrupt service routine : M[201]=244 M[101]=121 BADBAD GOODGOOD

5. Interrupts - concepts 5/27 Typical content (operation sequence) of interrupt service routine: 1. Storing working registers onto stack. 2. Precise recognition on interrupt cause. 3. Erasing interrupt. 4. Additional operations. 5. Restoring working registers from stack. 6. Interrupt system enable. 7. Return to interrupted program. cont. main program 3245671 main program INT IE

6. Interrupts - concepts 6/27 Example of incorrect structure of interrupt service routine: 1. assumption: interrupt system enabling (6) before erasing interrupt cause (3). 261 main programme 261 261 261 261 etc. INT IE

7. Interrupts - concepts 7/27 Examples of incorrect structure of interrupt service routine : 2. assumption: the absence of interrupt cause erasing (3): 245671 main program 245671245671 INT IE permanent, execution of interrupt service routine main program 245671245671 INT IE 245671 else with execution of the single instruction from main program

8. Interrupts - concepts 8/27 Examples of incorrect structure of interrupt service routine : INT IE cont. main program 324571 main program 3. assumption: the absence of interrupt system enabling (6):

9. Interrupts - concepts 9/27 Examples of incorrect structure of interrupt service routine : 4. assumption: incorrect restoring of the working registers from the stack (not equal numbers of writings and readings): execution of random codes 324576 main programm INT IE 1 Return address Reg. A Reg. B Reg. C stack : PC Return address Reg. A Reg. B Reg. C stack : PC

10. Interrupts - concepts 10/27 Interrupt system priority - urgency diversification of interrupts and their service routines. Realising by assignment of different priorities to interrupt sources. It’s particular case of tasks priority.

11. Interrupts - concepts 11/27 Realising of interrupt system priority: by hardware: - integrated controllers (MSI, LSI)... interrupt controller CPU I/O1I/O2I/On ass. priorities: n>..>2>1

12. ass. priorities : 1>2>...>n CPU I/O1I/O2I/On Vcc Interrupts - concepts 12/27 - or suitable connection structure (chain of interrupting devices);

13. Interrupts - concepts 13/27 Realising of interrupt system priority : by software - common beginning of interrupt service routines, acting as software interrupt system arbiter (recognise the sources of current active interrupts and decide about sequence of service)... CPU I/O1I/O2I/On Vcc

14. Interrupts - concepts 14/27... software interrupt system arbiter (SISA) with individual pooling CPU I/O1I/O2I/On Vcc cont. main program 4567132 SISA main program INT X

15. Interrupts - concepts 15/27... software interrupt system arbiter (SISA) with grouped pooling cont. main program 4567132 SI SA main program INT X CPU I/O1I/O2I/On Vcc

16. Interrupts - concepts 16/27 Multi-level interrupt system - current acting interrupt service routine can be suspended by new interrupt, usually of higher priority.

17. Interrupts - concepts 17/27 Vectorised interrupts – each source of IRQ has separate service routine executed directly after occuring the request. Vectorisation can be achieved by: additional specialized hardware controllers, exmp. 8259A; some microprocessors and many microcontrollers, exmp. Z80. No interrupt vectors = software arbitration.

18. Interrupts - concepts 18/27 Interrupts from different sources are asynchronous events - they occur quite independently CPU I/O1I/O2I/O3 Vcc INT instr. cycle #n+1instr. cycle #n interrupt sequence (“saw by CPU”): 1 i 3 (“simultaneously”), 2 INT1 INT2 INT3 INT instr. cycle #n-1 the moment of testing interrupt input by CPU

19. Interrupts systems 19/27 1. Single-level without priorities Features: time delays (  t 1,  t 2 ) of interrupt service routines; possibility of loss waiting for service interrupt; max. service delay can be sum of service times of other interrupts. System used in little systems with 1..2 interrupt sources. t1t1 2 1 2 3 t2t2 M P2 M P1 P2 P3 M interrupts requests

20. Interrupts systems 20/27 2. Single-level with priorities Features: more important interrupts will be served before others; possible time delay (  t 1,  t 2 ) of services; low-priority interrupts can have long time delay; possibility of loss waiting for service low-priority interrupt. System used with few number of interrupt sources. t2t2 2 3 1,2 t1t1 M P2 M P3 P2 P1 seeming simultaneous occur of interrupts 1 & 2 interrupts requests priorities: 3>2>1

21. Interrupts systems 21/27 3. Multi-level without priorities Features: immediate start of interrupt service routine; each interrupt service can be suspended (even for long time) by other interrupts. Rarely used system. 2 1 3 2 1 M P2 P1 M P3 P2 P1P2 P3 M interrupts requests

22. Interrupts systems 22/27 4. Multi-level with priorities Features: low-priority interrupts wait longer for service; more important interrupts are served faster. System recommended with higher number of interrupt sources. 2 1 1 2 3 M P2 P1 M P1 P2 P3 P2 P1 M interrupts requests priorities: 3>2>1

23. Interrupts - applications 23/27 Interrupt types - their applications 1. Clock interrupts - regular, constant frequency f > 1Hz: time interval measure (np. w ms); real time measure; in small microprocessor systems: service of basic I/O devices (keyboard, display, etc.).

24. Interrupts - applications 24/27 2. I/O devices interrupts - irregular, usually inform about: I/O device readines for new data transfer; finish transmission.

25. Interrupts - applications 25/27 3. From system supervising circuits - unique, usually have high priority - inform about special system states: power failure; parity error in memory block; software working cycle failure - watchdog; error/exception processor/coprocessor.

26. Interrupts - applications 26/27 4. Interrupt from process devices - irregular: inform about special events in controlled process: from alarm switch; overflow of allowed temperature, pressure, speed, etc.

27. Interrupts - applications 27/27 Task partitioning between main program and interrupt service routines