1. Functionality 3 2

2. The functionality of the block and the effectiveness of the use of the chip area

3. Example. Two-input LUT-s – 32 memory bits and 17 connections Let us realise the function f = abc + bcd + a b c AND OR a b c b c c d a Three-input LUT-s - 32 s memory bits and 13 connections OR AND a b c b c c d a b b Four input LUT-s - 16 memory bits and 5 connections a c b d

4. Logical blocks based on LUT-s LUT S MUX 0 1 S 0 1 T T Area of the logical block LBA = FA + (M BA 2 ) LBA –area of the logical block FA – fixee area M – number of LUT-s BA – area of the bit xx k

5. Geometrical model Logical block CL W RP X X CL + ( ) W RP X RP – Routing Piich Symmetrical FPGA. RALB = 2(CL W RP) + (W RP) 2 xxx RALB – Routing Area per LB Row Based FPGA. RALB = CL W RP xx Total area Total Area = N block (LBArea + RALB)

6. . The number of LUT bits is constantly 5. M=1 LUT IN1 IN5...... OUT M=2 LUT IN1 IN4...... LUT IN10 IN5 IN9...... MUX0 1 s OUT Logical blocks with decomposable LUT-s

7. M=4 LUT IN1 IN3 LUT IN13 IN2 MUX00 01 s0 s1 OUT Logical blocks with decomposable LUT-s II 10 11 LUT IN10 IN12 IN11 IN7 IN9 IN8 IN4 IN6 IN5 IN14

8. M=8 LUT IN1 LUT IN19 IN2 MUX000 001 s0 s1 s2 OUT Logical blocks with decomposable LUT-s III 010 011 LUT IN7 IN8 IN5 IN6 IN3 IN4 LUT IN9 LUT IN10 LUT IN15 IN16 IN13 IN14 IN11 IN12 100 101 110 111 IN17 IN18

9. Experimental results: Summary of the functionality and area-effectiveness of the logical block: 1.One-output LUT is the best while K=4 2.Pins waste area. The best solution is large functionality per pin. 3.LUT with several outputs is not effectual. 4.The best block based on PLA has 8-10 inputs, 12-13 terms and 3-4 outputs. 5.In case of decomposable LUT-s the best solution is M=4 6.Adding trigger to the logical block is effectual

10. Functionality of the logical block and its performance D tot = N l (D lb + D r ) D tot –total delay D lb – delay of the logical block D lb –delay of routing N l – number of logical blocks at the critical path x If functionality increases: 1.1. the number of levels (logical blocks) decreases at the path of the signals; 2.2. the delay of the logical blocks increases (bigger and more complex); 3.3. the total routing delay decreases; 4.4. total delay ?

11. Example. & & & & & & & & & & a b c d a c d a b c d a a b c d The logical blocks contain NAND elements with two outputs The logical blocks contain three-input LUT-s 2NAND delay 0,7 ns 3-LUT delay 1,4 ns Routing delay >0 LUT is swifter Two different realisations of the function f = a d b + a b c + a c d

12. 1.LUT with 5-6 inputs is good in case of a medium-sized routing delay 2.Low functional logical blocks (such as 2NAND) are not swift; 3.It is effectual to add the inversion possibility in case of simple logical blocks. 4.It is effectual to increase the number of terms from three to five in case of large AND-OR blocks Summary concerning the functionality and speed of the logical block

13. Summary 1.Logical blocks with a very low level of functionality are not good both from the point of view of speed and functionality; 2.Large functionality per output is good (e.g LUT-s) 3.The best LUT is with 4 inputs; 4.The best logical block from the point of view of area is the one where PLA structures are used; 5.Decomposable LUT-s can be effectual in solving some type of tasks; 6.Non-homogenuous structures can be more useful than homogenuous; 7.Hierarchical FPGA organisation may be more effective than a single-level organisation