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ECE 484 - Advanced Digital Systems Design Lecture 4 – Combinational Circuits in VHDL Capt Michael Tanner Room 2F46A 333-6766 HQ U.S. Air Force Academy.

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Presentation on theme: "ECE 484 - Advanced Digital Systems Design Lecture 4 – Combinational Circuits in VHDL Capt Michael Tanner Room 2F46A 333-6766 HQ U.S. Air Force Academy."— Presentation transcript:

1 ECE 484 - Advanced Digital Systems Design Lecture 4 – Combinational Circuits in VHDL Capt Michael Tanner Room 2F46A 333-6766 HQ U.S. Air Force Academy I n t e g r i t y - S e r v i c e - E x c e l l e n c e

2 Lesson Outline 1. Combinational vs. Sequential Circuits 2. Simple Signal Assignment 3. Conditional Signal Assignment 4. Selected Signal Assignment 5. Conditional vs. Selected Signal Assignment 6. Synthesis Guidelines 2

3 I n t e g r i t y - S e r v i c e - E x c e l l e n c e COMBINATIONAL VS. SEQUENTIAL CIRCUITS 3

4 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Combinational vs. Sequential Circuits Combinational circuit: No internal state Output is a function of inputs only No latches/FFs or closed feedback loop Sequential circuit: With internal state Output is a function of inputs and internal state Sequential circuit to be discussed later 4

5 I n t e g r i t y - S e r v i c e - E x c e l l e n c e SIMPLE SIGNAL ASSIGNMENT 5

6 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Simple Signal Assignment Simple signal assignment is a special case of conditional signal assignment Syntax: signal_name <= projected_waveform; y <= a + b + 1 after 10 ns; Timing info ignored in synthesis and δ-delay is used: signal_name <= value_expression; 6

7 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Simple Signal Assignment Example simple signal assignments status <= '1'; even <= (p1 and p2) or (p3 and p4); arith_out <= a + b + c - 1; Implementation of last statement: 7

8 I n t e g r i t y - S e r v i c e - E x c e l l e n c e BAD: Simple Assignment with Closed Feedback Loop A signal appears in both sides of a concurrent assignment statement q <= ((not q) and (not en)) or (d and en); Syntactically correct Forms a closed feedback loop (i.e., infinite loop) Should be avoided 8

9 I n t e g r i t y - S e r v i c e - E x c e l l e n c e CONDITIONAL SIGNAL ASSIGNMENT 9

10 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Conditional Signal Assignment Syntax Examples Conceptual implementation 10 signal_name <= value_expr_1 when boolean_expr_1 else value_expr_2 when boolean_expr_2 else value_expr_3 when boolean_expr_3 else... value_expr_n

11 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Example: 4-to-1 Multiplexer 11 library ieee; use ieee.std_logic_1164.all; entity mux4 is port( a,b,c,d: in std_logic_vector(7 downto 0); s: in std_logic_vector(1 downto 0); x: out std_logic_vector(7 downto 0) ); end mux4; architecture cond_arch of mux4 is Begin x <= a when (s="00") else b when (s="01") else c when (s="10") else d; end cond_arch;

12 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Example: 2-to-2 2 Binary Decoder 12 library ieee; use ieee.std_logic_1164.all; entity decoder4 is port( s: in std_logic_vector(1 downto 0); x: out std_logic_vector(3 downto 0) ); end decoder4; architecture cond_arch of decoder4 is begin x <= "0001" when (s="00") else "0010" when (s="01") else "0100" when (s="10") else "1000"; end cond_arch;

13 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Conceptual Implementation Syntax: signal_name <= value_expr_1 when boolean_expr_1 else value_expr_2 when boolean_expr_2 else value_expr_3 when boolean_expr_3 else... value_expr_n Evaluation in ascending order Achieved by “priority-routing network” Top value expression has a “higher priority” 13

14 I n t e g r i t y - S e r v i c e - E x c e l l e n c e 2-to-1 Mux Implementation 14 signal_name <= value_expr_1 when boolean_expr_1 else value_expr_2

15 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Cascaded Mux Implementation 15 signal_name <= value_expr_1 when boolean_expr_1 else value_expr_2 when boolean_expr_2 else value_expr_3 when boolean_expr_3 else value_expr_4

16 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Cascaded Mux Implementation 16

17 I n t e g r i t y - S e r v i c e - E x c e l l e n c e SELECTED SIGNAL ASSIGNMENT 17

18 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Selected Signal Assignment Syntax Examples Conceptual implementation 18 select_expression Discrete type or 1-D array With finite possible values choice_i A value of the data type Choices must be mutually exclusive all inclusive others can be used as last choice_i with select_expression select sig_name <= expr_1 when choice_1, expr_2 when choice_2, expr_3 when choice_3,... expr_n when choice_n;

19 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Example: 4-to-1 Multiplexer 19 Question: Can ‘ when “11” ’ be used to replace the ‘ when others ’ statement? architecture sel_arch of mux4 is begin with s select x <= a when "00", b when "01", c when "10", d when others; end sel_arch;

20 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Example: 2-to-2 2 Decoder 20 architecture sel_arch of mux4 is begin with s select x <= "0001" when "00", "0010" when "01", "0100" when "10", “1000" when others; end sel_arch;

21 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Example: Simple ALU 21 architecture sel_arch of simple_alu is signal sum: std_logic_vector(7 downto 0); signal diff: std_logic_vector(7 downto 0); signal inc: std_logic_vector(7 downto 0); begin inc <= std_logic_vector( signed(src0) + 1 ); sum <= std_logic_vector( signed(src0) + signed(src1) ); diff <= std_logic_vector( signed(src0) - signed(src1) ); with ctrl select result <= inc when "000"|"001"|"010"|"011", sum when "100", diff when "101", src0 and src1 when "110", src0 or src1 when others; -- "111“ end sel_arch; Question: Can “ 0-- ” be used to replace the first statement?

22 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Conceptual Implementation Achieved by a multiplexing circuit Abstract (k+1)-to-1 multiplexer sel is with a data type of (k+1) values: c0, c1, c2,..., ck select_expression is with a data type of 5 values: c0, c1, c2, c3, c4 22 with select_expression select sig <= value_expr_0 when c0, value_expr_1 when c1, value_expr_n when others;

23 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Conceptual Implementation 23

24 I n t e g r i t y - S e r v i c e - E x c e l l e n c e CONDITIONAL VS. SELECTED SIGNAL ASSIGNMENT 24

25 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Conditional vs. Selected Signal Assignment Conversion between conditional vs. selected signal assignment Comparison 25

26 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Conversion: Selected → Conditional 26 with sel select sig <= value_expr_0 when c0, value_expr_1 when c1|c3|c5, value_expr_2 when c2|c4, value_expr_n when others; sig <= value_expr_0 when (sel=c0) else value_expr_1 when (sel=c1) or (sel=c3) or (sel=c5) else value_expr_2 when (sel=c2) or (sel=c4) else value_expr_n;

27 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Conversion: Conditional → Selected 27 sig <= value_expr_0 when bool_expr_0 else value_expr_1 when bool_expr_1 else value_expr_2 when bool_expr_2 else value_expr_n; sel(2) <= '1' when bool_exp_0 else '0'; sel(1) <= '1' when bool_exp_1 else '0'; sel(0) <= '1' when bool_exp_2 else '0'; with sel select sig <= value_expr_0 when "100"|"101"|"110"|"111", value_expr_1 when "010"|"011", value_expr_2 when "001", value_expr_n when others,

28 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Conditional vs. Selected Comparison 28 Selected signal assignment: Good match for a circuit described by a functional table Example: binary decoder, multiplexer Less effective if input pattern is given a preferential treatment Conditional signal assignment: good match for a circuit a circuit that needs to give preferential treatment for certain conditions or to prioritize the operations Example: priority encoder May “over-specify” for a functional table based circuit. Can handle complicated conditions. pc_next <= pc_reg + offset when (state=jump and a=b) else pc_reg + 1 when (state=skip and flag='1') else...

29 I n t e g r i t y - S e r v i c e - E x c e l l e n c e SYNTHESIS GUIDELINES 29

30 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Synthesis Guidelines 30 Avoid a closed feedback loop in a concurrent signal assignment statement. Think of the conditional signal assignment and selected signal assignment statements as routing structures rather than sequential control constructs. The conditional signal assignment statement infers a priority routing structure, and a larger number of when clauses leads to a long cascading chain. The selected signal assignment statement infers a multiplexing structure, and a large number of choices leads to a wide multiplexer.

31 I n t e g r i t y - S e r v i c e - E x c e l l e n c e Lesson Outline 1. Combinational vs. Sequential Circuits 2. Simple Signal Assignment 3. Conditional Signal Assignment 4. Selected Signal Assignment 5. Conditional vs. Selected Signal Assignment 6. Synthesis Guidelines 31

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