1. Karan Maini and Sriharsha Yerramalla ECE 753 Project #10 May 1, 2014 Tool for Customizing Fault Tolerance in a System

2. Agenda Introduction Background and Related Work Problem Statement Formulation Implementation Hardware Redundancy Techniques and FT Library Synthesis Results – Area and Timing Conclusion and Future Scope 2

3. CAD Tools −Implementing electronic systems easier −Cut down on development time −Made verification process automated CAD Tools for Fault Tolerance −Did not leverage advancements −Fault Tolerance was introduced manually −Being picked up in the recent past 3 Introduction

4. Need for Fault Tolerance −Real-time Systems −Operation Critical Systems −No guarantee of flawless execution Applications −Banking −ATM Machines −Spacecraft −Satellites 4 Introduction

5. There has been several attempts made to develop an efficient tool without much manual intervention to introduce FT. This could be at various levels of granularity. Our attempt is to make FT at module level granularity. 5 Introduction

6. 6 The Challenge IJ A B C D F E H G J K M

7. 7 The Plan IJ A B C D F E H G J K M

8. 8 The Plan IJ A B C D F H G J K M

9. 9 Solution A B C J K V V BBB

10. Agenda Introduction Background and Related Work Problem Statement Formulation Implementation Hardware Redundancy Techniques and FT Library Synthesis Results – Area and Timing Conclusion and Future Scope 10

11. Hardware Redundancy −Insertion of F-T components into circuit −Done Manually (Old days) −Automatic Insertion Tools (At Present) Process −Identify element(s) to be modified −Replication of selected element(s) −Selecting one set of output from different outputs coming from replicated element(s) 11 Background and Related Work

12. Hardware Redundancy (Contd.) −Initial Conditions – Input synthesizable design files −Pre-processing tasks – Identify type, number of elements present and their characteristics −Similar to simplified elaboration for synthesis −Specify the Hardware Redundancy technique to be followed 12 Background and Related Work

13. Information Redundancy −Selection of elements (Memory – IM, DM, Register Files) −Nearly entire module modification to deal with −Modification of data types and operators in order to process encoded information −Insertion of encoders, decoders and checkers in original design −Adding appropriate operators in F-T library −Declaration of target objects with the extra bits 13 Background and Related Work

14. Information Redundancy (Contd.) −Insert an encoder at a selected point −Extend the size of selected data to accommodate extra bits required by the redundant code used −Perform the functionality on the coded data −Insert a decoder/checker at a selected output point to get back the original data 14 Background and Related Work

15. Agenda Introduction Background and Related Work Problem Statement Formulation Implementation Hardware Redundancy Techniques and FT Library Synthesis Results – Area and Timing Conclusion and Future Scope 15

16. Make a design Fault Tolerant by introducing components into the design using various Hardware Redundancy Techniques. Provide a Fault Tolerant Library to choose components from. Synthesize the original and new design to compare overhead introduced in terms of area and time. 16 Problem Statement Formulation

17. Introduce Fault tolerance at Modular level Target for Coarse granularity 17 Aim

18. 18 Assumptions User will input all the Synthesizable design files At any given instant of time, only a single instance of a module may be fault prone. User will only input files written in Verilog HDL

19. Agenda Introduction Background and Related Work Problem Statement Formulation Implementation Hardware Redundancy Techniques and FT Library Synthesis Results – Area and Timing Conclusion and Future Scope 19

20. 20 Taming the Bull In which stage of design should this be tackled? RTL or netlist In netlist – Finer control over granularity, but higher design complexity In RTL – Difficult to have smaller granularity, but relatively simple design This is where our tool helps

21. 21 Approach Accept design files and top level module from user. Identify different modules and their hierarchies present in the design. Accept options from user. Update the design with fault tolerance. Verify the design.

22. 22 Design Scheme of Fault Tolerant Insertion Tool

23. 23 Front End - GUI Technology: Java SwingLook and Feel: Windows 8

24. 24 Section 1 Welcome Screen Upload Design files View/Update selected files Enter top-level module Fork() a child process to call back-end search engine

25. 25 Section 2 Hierarchical View Returns from back-end JTree Component used Different levels – modules and instantiations Singleton selection on leaf node - select an instance

26. 26 Section 3 Select Redundancy Type Scan characteristics of Instantiated Module  Parameters passed  Bus-width of parameters Introduction of Library Component into design Success Message Dialog Box to inform user

27. 27 Logical Components of Tool GUI FT Insertion Library Search Engine Front EndBack End

28. Search Engine block FT insertion block passes the Verilog design files to search engine block. Searches for all modules in the design and populates them in an array. Starts a recursive process to identify all the instances and their hierarchies. Returns the hierarchical information to FT insertion. 28

29. Library Following hardware redundancies are supported. 1.TMR 2.5MR 3.Hybrid 4.Sift-out 5.Pair and Spare 29

30. 30 TMR Instance is replicated thrice and a Voter is added. Parameterized voter to support any bus width ALU1 ALU2 ALU3 Voter

31. Similar to TMR Voter…. 31 5MR ALU2 ALU3 ALU4 Vot er ALU5 ALU1

32. Hybrid Redundancy Implemented the design proposed by Daniel P. Siewiorek et al. Made minor modifications to circuit to support scalability. 32

33. 33 Implementation of Hybrid Redundancy P P P S Status reg Comp block Voter S

34. Sift-Out Modular Redundancy Implemented the design proposed by Paulo T. De Sousa et al. Made minor modifications 34

35. Implementation of Sift-out Redundancy 35 comparatorand register EC P1 P2 P3

36. Pair and Spare 36 comparator Switch P1 P2 P3 P4

37. Library Options 37

38. Area and Delay Overhead 38

39. Micro-op Generator 39 FSM D Data Path Micro-op inst gen Inst_gen Offset_reg_num_gen Offset_gen Reg_num_gen ALD Priority Encoder ALD

40. Area Overhead for Micro-op Generator 40 Area without FT – 7628.1 Module / FT technique 5MR Hybrid (3,2) Sift-out (5) Data_path 28023.1 28220.7 28214.2 FSM11215.311420.811415.7 Offset_Regnum gen 17925.618128.218123.4 Reg_Num_Gen16968.41721217205.3 Act low decoder8378.18661.98656

41. DUTs PIIR filter Micro-op Generator 5 stage pipelined micro-processor 41

42. Future Work Other types of hardware redundancies can be added to library modules without changing other parts of tools. Information redundancy can also be added, but it will involve change in the tool and will need more information from user. 42

43. Conclusion Tool that introduces fault tolerance in a Digital System is successfully developed. The tool is tested on three different designs. Overhead of various fault tolerance techniques is calculated and compared. 43

44. Tools Used Java Perl Design Vision Quartus 44