1. TANNENBAUM SECTION 2.3 INTERPROCESS COMMUNICATION OPERATING SYSTEMS

2. MULTIPROGRAMMING CONUNDRUM Environment consists of concurrent processes Each process (and thread) is running, ready, or blocked. Processes are asynchronous May be started at any time. Problem: How to arrange for orderly access to shared, modifiable memory

3. PARBEGIN/PAREND Control structure to model parallelism parbegin indicates that execution splits into parallel execution sequences, each with its own thread of control (and pcb if a process) Each sequence eventually terminates and reaches parend Sequential execution resumes

4. EXAMPLE pgmX() { struct commonMem; parbegin { proc0; proc1; } parend } Upon reaching parbegin, both proc0 and proc1 start. Both have access to commonMem

5. HEIDI AND PAUL AT THE BANK proc0( ) proc1( ) { read request;  pc read request; if (acctRec >= request) if (acctRec >= request) acctRec = acctRec – request; acctRec = accRec-request;  pc else else display (“error”); display(“error”); } 1.acctRec = 100 2.proc1 goes first and requests 75 3.Context switch after test 4.proc0 runs and requests 75 5.proc 0 runs to completion 6.Will proc1 get his money?

6. RACE CONDITION Two or more processes reading or writing shared memory Result depends on who gets there first

7. CRITICAL SECTION Shared modifiable memory Process accessing shared modifiable memory is in its critical section Goal is to allow only orderly access to the critical section

8. REQUIREMENTS FOR SHARED COOPERATING PROCESSES 1.Mutual Exclusion No two processes may be simultaneously in their critical sections 2.Speed No assumptions may be made about the relative speeds of processes or number of cpus 3.Authority No process, in any state, outside of its critical section may block other processes 4.Postponement Processes may not be indefinitely prevented from entering their critical sections

9. SOLUTION 1: DISABLE INTERRUPTS Two processes run in parallel Problem: context switches come from asynchronous interrupts Solution: disable interrupts (tinkertoy solution)

10. RESULT After process enters CS, no context switch occurs 1.Mutual exclusion is achieved 2.Speed achieved 3.Authority achieved 4.Indefinite postponement not achieved What if disabling process fails: interrupts are not resumed What if CS is arbitrarily long?

11. SOLUTION 2: LOCK VARIABLE Single lock variable Available to both processes Set to 1 when a process is in CS Set to 0 when no process is in CS lock pr0 pr1

12. THE LOCK MODEL lock_var() { int lock = 0; int lock = 0; parbegin parbegin { proc0(); proc0(); proc1(); proc1(); } parend parend}proc0(){ while(1) while(1) { while (lock);//wait while (lock);//wait lock = 1; //lock the door lock = 1; //lock the door crit_sect(); crit_sect(); lock = 0; //unlock door lock = 0; //unlock door non_crit_sect() non_crit_sect() }}proc1(){ while(1) while(1) { while (lock);//wait while (lock);//wait lock = 1; //lock the door lock = 1; //lock the door crit_sect(); crit_sect(); lock = 0; //unlock door lock = 0; //unlock door non_crit_sect() non_crit_sect() }}

13. FAILS MUTUAL EXCLUSION 1. proc0 reads lock (lock = 0) 2. proc0 passes mutex gate but has not set lock 3. Context switch 4. proc1 reads lock (which is still 0) 5. proc1 sets the lock and enters CS 6. Context switch 7. proc0 sets the lock and enters the CS

14. SOLUTION 3: SPIN LOCK (TURN VARIABLE) Key Features Lock indicates turn rather than presence in critical section proc continuously tests lock to see if it’s turn to use CS has come Continuous testing: busy waiting Lock that uses busy waiting: spin lock pr0 pr1 Turn

15. THE SPIN LOCK MODEL turn_var() { int turn = 0; int turn = 0; parbegin parbegin { proc0(); proc0(); proc1(); proc1(); } parend parend}proc0(){ while(1) while(1) { while (turn != 0);//wait while (turn != 0);//wait critSect(); critSect(); turn = 1; //proc1’s turn turn = 1; //proc1’s turn non-critSect(); non-critSect(); }}proc1(){ while(1) while(1) { while (turn != 1);//wait while (turn != 1);//wait critSect(); critSect(); turn = 0; //proc0’s turn non-critSect(); turn = 0; //proc0’s turn non-critSect(); }}

16. ACHIEVES MUTUAL EXCLUSION PRICE IS STRICT ALTERNATION 1. proc1 runs. turn = 0, so waits 2. Context switch 4. proc0 runs. turn = 0, so enters CS 5. Context switch 5. proc1 runs. turn = 0 so waits 6. Context switch 7. proc0 runs. leaves CS. sets turn to 1 8. Context switch 9. proc1 runs and enterers CS

17. FAILS CRITICAL SECTION PROBLEM AUTHORITY Suppose non-cs for proc0 is short Suppose non-cs for proc1 is long Suppose proc1 in non CS proc0 enters CS because proc1set turn to 0 proc0 in non CS proc0 finishes non CS and is ready to enter CS proc1 is still in non CS but because it has not finished it is outside its CS but blocking another process from entering its own CS.

18. SUMMARY 1.Disable Interrupts: Violates indefinite postponement Problem: if disabling process fails, the other process is indefinitely postponed 2.Single Lock Variable: violates mutual exclusion Problem: context switch between test and set 3.Spin Lock (Turn Variable): violates authority Problem: one process could be waiting for the other to finish its (very long) non-critical section.

19. FIX 1 FOR SOLUTION 2 Modify solution 2 so that it uses two turn variables turn_0 set when 0 runs turn_1 set when 1 runs

20. THE REVISED TURN MODEL lock_var() { int turn_0 = 0; int turn_0 = 0; int turn_1 = 0; int turn_1 = 0; parbegin parbegin { proc0(); proc0(); proc1(); proc1(); } parend parend}proc0(){ while(1) while(1) { while (turn_1); while (turn_1); turn_0 = 1; turn_0 = 1; crit_sect(); crit_sect(); turn_0 = 0; turn_0 = 0; }}proc1(){ while(1) while(1) { while (turn_0); while (turn_0); turn_1 = 1; turn_1 = 1; crit_sect(); crit_sect(); turn_1 = 0; turn_1 = 0; }}

21. VIOLATES MUTUAL EXCLUSION proc0 tests turn_1: false context switch proc1tests turn_0: false proc1 sets turn_1 to true and enters critical section proc_0 sets turn_0 and enters critical section Problem: Once process does while test, it must be assured that the other process can’t proceed past its own while test Fix 2 for Solution 2: set flag before test

22. THE REVISED TURN MODEL lock_var() { int turn_0 = 0; int turn_0 = 0; int turn_1 = 0; int turn_1 = 0; parbegin parbegin { proc0(); proc0(); proc1(); proc1(); } parend parend}proc0(){ while(1) while(1) { turn_0 = 1; turn_0 = 1; while (turn_1); while (turn_1); crit_sect(); crit_sect(); turn_0 = 0; turn_0 = 0; }}proc1(){ while(1) while(1) { turn_1 = 1; turn_1 = 1; while (turn_0); while (turn_0); crit_sect(); crit_sect(); turn_1 = 0; turn_1 = 0; }}

23. VIOLATES INDEFINITE POSTPONEMENT proc0 sets turn_0 to true context switch proc1 sets turn_1 to true proc1 tests turn_0 and waits context switch proc0 tests turn 1 and waits Deadlock-each of two processes is waiting on something that other has