1. An Object-Oriented Internet-based Framework for Chip Package Thermal & Stress Simulation IPACK2001-15810 Shinko Electric Industries Co., Ltd. 2 Package Design Center Nagano, Japan www.shinko.co.jp InterPACK'01 The Pacific Rim/ASME International Electronic Packaging Technical Conference and Exhibition July 8–13, 2001, Kauai, Hawaii, USA Georgia Tech 1 Engineering Information Systems Lab eislab.gatech.edu 1 Russell S. Peak, 2 Ryuichi Matsuki, 1 Miyako W. Wilson, 1 Donald Koo, 1 Andrew J. Scholand, 2 Yukari Hatcho, 1 Sai Zeng

2. 2 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Phase 1 Summary - Shinko Project

3. 3 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Chip Package Products Shinko Plastic Ball Grid Array (PBGA) Packages Quad Flat Packs (QFPs)

4. 4 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Traditional VTMB FEA Model Creation Manually Intensive: 6-12 hours FEA Model Planning Sketches - EBGA 600 Chip Package VTMB = variable topology multi-body

5. 5 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Outline u Analysis Integration Background –CAD-CAE Interoperability Research & Development u Chip Package Analysis Tool Overview u On Automating Variable Topology Multi-Body (VTMB) FEA Problems u Summary

6. 6 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC X-Analysis Integration Techniques X = Design, Mfg., Sustainment, … a. Multi-Representation Architecture (MRA)b. Explicit Design-Analysis Associativity c. Analysis Module Creation Methodology

7. 7 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC An Introduction to X-Analysis Integration (XAI) Short Course Outline Part 1: Constrained Objects (COBs) Primer –Nomenclature Part 2: Multi-Representation Architecture (MRA) Primer –Analysis Integration Challenges –Overview of COB-based XAI Part 3: Example Applications »Airframe Structural Analysis (Boeing) »Circuit Board Thermomechanical Analysis (DoD: ProAM; JPL/NASA) »Chip Package Thermal Analysis (Shinko) –Summary Part 4: Advanced Topics & Current Research

8. 8 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Outline u Analysis Integration Background –CAD-CAE Interoperability Research & Development u Chip Package Analysis Tool Overview u On Automating Variable Topology Multi-Body (VTMB) FEA Problems u Summary

9. 9 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Tool Usage Overview Preliminary Design Analysis Module Setup & Usage Automated FEA Meshing & Solution Thermal ResultsDocumentation Assistance 1 2a 2b 3a3b

10. 10 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Flexible High Diversity Design-Analysis Integration Electronic Packaging Examples: Chip Packages/Mounting Shinko Electric Project: Phase 1 (completed 9/00) EBGA, PBGA, QFP Analysis Modules (CBAMs) of Diverse Behavior & Fidelity FEA Ansys General Math Mathematica Analyzable Product Model XaiTools ChipPackage Thermal Resistance 3D3D Modular, Reusable Template Libraries Analysis Tools Design Tools PWB DB Materials DB* Prelim/APM Design Tool XaiTools ChipPackage Thermal Stress Basic 3D** ** = Demonstration module Basic Documentation Automation Authoring MS Excel

11. 11 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Using Internet/Intranet-based Analysis Solvers Thick Client Architecture Client PCs XaiTools Thick Client Users Internet June’99-Present: EIS Lab - Regular internal use U-Engineer.com - Demo usage: - US - Japan Nov.’00-Present: Electronics Co. - Began production usage (dept. Intranet) Future: Company Intranet and/or U-Engineer.com (commercial) - Other solvers Iona orbixdj Mathematica Ansys Internet/Intranet XaiTools Ansys Solver Server XaiTools Ansys Solver Server XaiTools Math. Solver Server CORBA Daemon XaiTools Ansys Solver Server FEA Solvers Math Solvers CORBA Servers CORBA IIOP... Self-Serve Engineering Service Bureau (ESB) Server Machines

12. 12 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC APM Design Tool Preliminary Design of Packages - PBGA Screens APM = analyzable product model

13. 13 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Example Chip Package Idealizations (PBGA) Idealization for solder-joint/thermal ball Idealization for thermal via Courtesy of Shinko - see [Koo, 2000]

14. 14 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Generic COB Browser with design and analysis objects (attributes and relations) Customized Analysis Module Tool with idealized package cross-section COB-based Analysis Template Typical Input Objects for EBGA Thermal Resistance Module COB = constrained object

15. 15 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC COB-based Analysis Template Typical Highly Automated Results FEA Temperature Distribution Thermal Resistance vs. Air Flow Velocity Auto-Created FEA Inputs (for Mesh Model) Analysis Module Tool COB = constrained object

16. 16 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Test Cases - Shinko Auto-Generated FEA Mesh Model of PBGA 256 with Thermal Vias FEA mesh model with strong inter-body coupling 29 idealized bodies 10 idealized materials 1 main pattern ~3 sub patterns Small Idealized Vias Thin Copper Layers

17. 17 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Results Validation Thermal resistance Good comparisons: (a) simulation via VTMB algorithm (in XCP) (b) simulation via traditional manual approach (c) physical measurements (a) (b) (c)

18. 18 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Outline u Analysis Integration Background –CAD-CAE Interoperability Research & Development u Chip Package Analysis Tool Overview u On Automating Variable Topology Multi-Body (VTMB) FEA Problems u Summary

19. 19 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Traditional VTMB FEA Model Creation Manually Intensive: 6-12 hours FEA Model Planning Sketches - EBGA 600 Chip Package VTMB = variable topology multi-body

20. 20 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC 1 2 3 1 2 3 1 2 4 1a 2 3a 1b 1c 3b3c 3a3b 2 1a1b1c 1d1e 3 1a1b 1c 1d 2 3 4a4b4c Idealized Analytical BodiesDecomposed FEA Geometry Models original topology change (no body change) body change (includes topology change) Variable Topology Multi-Body (VTMB) FEA Meshing Challenges Labor-intensive “chopping” Meshing & Solving Design Model

21. 21 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Product Information-Driven FEA Methodology Purpose of VTMB Methodology algorithm ij Design Types i = 1…m Analysis Types j = 1…n Design Instances Analysis Instances VTMB FEA Models VTMB Methodology create algorithm ij once for a given ijj  {1…n} (not all design types have all analysis types) e.g.) for i=1(EBGA), j=1(thermal resistance) j=2 (thermal stress) for i=2 (PWB), j=1 (warpage) Chip package APMsthermal resistance CBAMs PWB APMs thermal stress CBAMs ANSYS SMMs VTMB= variable topology multi-body use algorithm ij many times

22. 22 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Methodology Scope of VTMB algorithm ij for cbam ij Conditions & Next-Higher CBAMs Boundary Condition Objects & Discipline Analyzable Product Model Part Feature & Assembly Structure Behavior/Mode MoS allowable actual Objectives Analysis Context Context-Based Analysis Model (CBAM) idealizations,  allowables Step 1a boundary variables Step 1b Associativity Linkages,  Step 4 Pseudo-Analysis Building Blocks (pseudo-ABBs) Analysis Subsystems Solution Method Models (SMMs) transformations,  Step 2 Step 3 VTMB algorithm ij for cbam ij [Koo, 2000] [Tamburini, 1999] [Peak, 2001]

23. 23 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Design Changes with Large Topology Impact Example Variations: PBGAs & EBGAs EBGA 600 with 2 Steps EBGA 325 with No Steps PBGA 313 with Thermal Vias & Thermal Balls 2D partial views of 3D models

24. 24 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Idealized Analytical Models FEA Mesh Models thin & largethick & small 2D partial views of 3D models z-direction topology changes Design Change with Small Topology Impact Heat Spreader Size Variations - EBGA 600

25. 25 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Test Cases - Shinko Auto-Generated FEA Model: QFP PCDPH FEA mesh model with strong inter-body coupling 23 idealized bodies 9 idealized materials 1 main pattern ~3 sub patterns

26. 26 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Design Changes with Large Topology Impact Example Variations: QFPs QFP 128 SL Die Pad QFP 208 DPH HS/Tape 2D partial views of 3D models

27. 27 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Basic Stress Analysis Module Tool Highly automated FEA model creation Re: thermal model: Same APM (but different idealizations) CORBA-based solvers, etc. Pattern-based meshing Adjustable mesh density PBGA 625

28. 28 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Multi-Fidelity Idealizations Mode-dependent Idealized Geometries; Same Dimension Thermal Resistance Thermal Stress FEA ModelIdealized Geometry (3D) Common Design Model FEA Model Idealized Geometry (3D)

29. 29 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Outline u Analysis Integration Background –CAD-CAE Interoperability Research & Development u Chip Package Analysis Tool Overview u On Automating Variable Topology Multi-Body (VTMB) FEA Problems u Summary

30. 30 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Pilot & Initial Production Usage Results Product Model-Driven Analysis u Reduced FEA modeling time > 10:1 (days/hours  minutes) u Reduced simulation cycle > 75% u Enables greater analysis intensity  Better designs u Leverages XAI / CAD-CAE interoperability techniques –Objects, Internet/web services, ubiquitization methodology, … References [1] Shinko 5/00 (in Koo, 2000) [2] Shinko evaluation 10/12/00 VTMB = variable topology multi-body technique [Koo, 2000]

31. 31 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC

32. 32 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Summary of Tools and Services offered via Georgia Tech Research Corp. http://eislab.gatech.edu/ u XaiTools FrameWork ™ –General-purpose analysis integration toolkit u Product-Specific Toolkits –XaiTools PWA-B ™ –XaiTools ChipPackage ™ u U-Engineer.com ™ –Internet-based engineering service bureau (ESB) –Self-serve automated analysis modules  Full-serve consulting  Research, Development, and Consulting –Analysis integration & optimization – Short courses –Product-specific analysis module catalogs –Internet/Intranet-based ESB development –Knowledge-based engineering & information technology »PDM, STEP, GenCAM, XML, UML, Java, CORBA, Internet, … –CAD/CAE/CAM, parametric FEA, thermal & mechanical analysis

33. 33 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC For Further Information... u EIS Lab web site: http://eislab.gatech.edu/http://eislab.gatech.edu/ –Publications, project overviews, tools, etc. –See: Publications  DAI/XAI  Suggested Starting Points X-Analysis Integration (XAI) Technology http://eislab.gatech.edu/pubs/reports/EL002/ http://eislab.gatech.edu/pubs/reports/EL002/ u XaiTools ™ home page: http://eislab.gatech.edu/tools/XaiTools/http://eislab.gatech.edu/tools/XaiTools/ u Pilot commercial ESB: http://www.u-engineer.com/http://www.u-engineer.com/ –Internet-based self-serve analysis –Analysis module catalog for electronic packaging –Highly automated front-ends to general FEA & math tools

34. 34 Georgia Tech  Engineering Information Systems Lab  eislab.gatech.edu © 1993-2001 GTRC Nomenclature