1. 1 SystemVerilog Enhancement Requests Daniel Schostak Principal Engineer February 26 th 2010

2. 2 Contents 1. Introduction 2. Efficiency Enhancements 3. Expressiveness Enhancements 4. Construct / Language Enhancements 5. Examples of Ambiguities 6. Conclusion

3. 3 Introduction  What is ARM’s interest in SystemVerilog?  It is one of the Hardware Verification Languages that we use  What does ARM use SystemVerilog for?  Constrained Random Verification  Functional Coverage  High Level Assertions for Formal Verification  What is my involvement with SystemVerilog?  Co-developed methodology and associated internal class library for constrained random verification  Developer of constrained random SystemVerilog testbench (execution unit for an ARMv7-A CPU)  Verification Lead for ARMv7-A CPU project with SystemVerilog as main HVL from initial development to tape-out

4. 4 Efficiency Enhancements 1. Ability to copy pointers to arrays (currently have to wrap array with class so can copy object handle) 2. Ability to copy pointers to functions (currently have to wrap function with class so can copy object handle) 3. Ability to pass expressions to const ref function arguments (extension of http://www.eda.org/svdb/view.php?id=2349)http://www.eda.org/svdb/view.php?id=2349 4. If object being randomized contains empty list/null object, constraints that would apply to objects in list/non-null object should not be considered (cannot know what constraints object instance itself would have)

5. 5 Expressiveness Enhancements 1. Chain function invocations (http://www.eda.org/svdb/view.php?id=2735)http://www.eda.org/svdb/view.php?id=2735 2. Allow declarations at any point in a block statement rather than only at the beginning (otherwise end up creating dummy block statements) 3. Use of new() in non-declaration contexts (e.g. q.push_back(new) or q.push_back(new )) 4. new with { … } (otherwise have to explicitly create constructor that provides this behaviour) 5. “others” in distribution constraints (otherwise end up specifying blanket range including values already specified hoping this does not skew distribution) 6. No specific order requirement for keywords in declarations

6. 6 Class Construct Enhancements 1. Some way of deriving class from multiple parents  Aspect Oriented Programming  C++ Multiple Inheritance  Java style interfaces (class can implement multiple interfaces) 2. Some way to document and enforce overriding restrictions  Parent class specifies derived class cannot override function  Derived class specifies not overriding function in parent class 3. Parse function implementations in parameterized classes only if implementation is used 4. Allow use of import with static identifiers declared in class (e.g. enumerated type identifiers) 5. Friend classes 6. Provide equivalent of final block for class declarations

7. 7 Hierarchy Related Enhancements 1. Treat hierarchical references to parameter values as elaboration time constants (facilitate parameter sharing – see http://www.eda.org/svdb/view.php?id=1058)http://www.eda.org/svdb/view.php?id=1058 2. SystemVerilog event variable can be used as pointer to Verilog static event (allows decoupling of hierarchy in similar way to virtual interfaces) 3. Ability to refer to global namespace from inside package (avoid package proliferation) 4. Ability to “import” signal declarations from scope bound to (avoid explicit port list when binding module of assertions) 5. Allow use of modports when instantiating interfaces with bind directives 6. Syntax for lexical scope references in bind directive

8. 8 Miscellaneous Enhancements 1. Variable width part selects (http://www.eda.org/svdb/view.php?id=2684)http://www.eda.org/svdb/view.php?id=2684 2. Allow casting_type to be compile time constant expression (in particular class parameter value) 3. Ability to use.* for parameter value assignments (special case of http://www.eda.org/svdb/view.php?id=98)http://www.eda.org/svdb/view.php?id=98 4. Reopening of packages (http://www.eda.org/svdb/view.php?id=2961)http://www.eda.org/svdb/view.php?id=2961 5. System task for determining seed simulation started with (useful for constructing unique file names) 6. More specific `__FILE__ type compiler directives  `__CLASS__ in form of string literal  `__FUNCTION__ in form of string literal

9. 9 Examples of Ambiguities 1. Elaboration order of bind directives (e.g. bind interfaces into DUT and then reference bound interfaces in succeeding bind directive; can also have effect on random stability) 2. Format of $typename return value should be standardized 3. Order of randomization method invocations if randomizing nested objects 4. Should default argument be repeated in class method out-of-block declaration? 5. Result of $sformatf(“%0 b”, value) if value[ ] === x (is string representation padded with leading zero?) 6. Should.name() for escaped identifier include “\”? 7. Should $value$plusargs(“ =%s”, value) set value to “” or “0” for + = / + =“”?

10. 10 Conclusion  Top Five Enhancements 1. Ability to derive class from multiple parents 2. Copy pointers to arrays 3. Expressiveness enhancements 4. Ambiguity resolution 5. Extend support for generic programming