1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI Design Jacob Maxa Results of Phase 3: ST65 Netlist 13.12.2012 Institute MD, University of Rostock

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 2 Challenge Create a Verilog netlist for the ST65 technology –Build upon NAND/NOR gatter –65 nm structure width Optimize design for the ST65 technology –Change adder types for 10, 13 and 14 bit width –Carrylookahead –Brent-Kung –Ripple Carry

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 3 Calculations Postsynthesis

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Calculations Finals Slide 4 P dyn = 1 µW P stat = 1 mW area = 3k VDD = 1,0 V

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Calculations Finals Slide 5 P dyn = 1 µW P stat = 1 mW area = 6k VDD = 1,3 V

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 6 Synopsys Flags Flags optimize_registers – move registers to decrease the negative slack set_ungroup your_filter – unfold the hierarchical structures set_flatten true -design your_filter -effort high –minimize multiple_output -phase true set_structure true -design your_filter -boolean true -boolean_effort high -timing true set_max_area 3000 -ignore_tns set_max_leakage_power 1 mW set_max_dynamic_power 1 uW set_cost_priority {max_delay min_delay max_capacitance max_transition cell_degradation max_fanout} Compiling compile -map_effort high -power_effort high -ungroup_all -boundary_optimization –scan - auto_ungroup delay compile_ultra -incremental -retime

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 7 Results (1/2) Mandatory values for FGPAMandatory values for ASIC UnitSynthesis Backannotati on UnitST65 (metric)ST65 (speed) Frequency fMHz365,23318,066MHz250,982400 Area A# LUT-FF pair233182μm 2 3594,75994882,2799 # Pipeline Stages 133133 Metric MHz/# LUT- FF pair 1,56751,7476 J -2 = W -2 s -2 = s 4 /(kg 2 m 4 ) 5,4253*10 27 4,0844*10 25

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 8 Results (2/2)

9. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock End Thanks for your attention! Questions? Slide 9