1. Implementing Click IP Router Kernel on VLIW Architectures Kanyu Mark Cao and Xiaodong Jin Many thanks to Scott Weber and Kees Vissers for the help on this project

2. Outline Application Click IP router Architectures Trimedia TM1300 TMS320C6000 Comparison Performance Codesize

3. Click IP Router Modular Design Easy to Configure Reasonable Performance Originally implemented in C by Scott Weber, modifications were made for each processor

4. Implemenation Element LookupIPRoute Trie-based route table lookup IP packet traffic and route table Generated randomly Complier and simulator downloaded TI code-composer from TI webpage Trimedia SDE2.1 provided by Kees Vissers

5. Trimedia TM1300 Processor Central Processing Unit 5 slot wide VLIW 143 or 166 MHz Variable instruction length 27 pipelined function unit 128 32-bit registers 32 special/SIMD ops Memory System 143 MHz 32-bit bus 512KB to 64MB Caches 8-way set associative with LRU replacement 64 bytes block size Data 16KB/Instruction 32KB

6. SDE 2.1 for TM1300  A anis-compliant C/C++ optimizing compiler  A cycle-accurate, machine level simulator  A source level debugger  Profiling and performance analysis tools  Support profile driven compilation  Have option to switch off the memory model

7. TI TMS320C6701 Processor

8. More about TMS320C6701  167MHz  1336 MIPS and 1 GFLOPS Executes up to 8 instructions in single cycle (6 float, 2 integer)  On-chip 128K RAM (data 64KB/Instruction 64KB)  Thirty-two 32-bit registers  Single-cycle IEEE floating point (single precision)

9. Results of Trimedia TM1300

10. Results of TI TMS320C6701 Speed= 140k Packets/Sec

11. Comparison between the two VLIW Processors Trimedia TM1300TI TMS320C6701 Clock Speed166MHz167MHz Slot Wide58 Routing Speed (Perfect Memory) Packets/Sec

12. Other Processors (by Scoot Weber and Fernando De Bernardinis) ARM SA-110 Recommended by Intel for routers 233.5 MHz 32-bit StrongARM 32-way set-associative caches HPL-PD EPIC 7 slot wide VLIW 16 K 2-way write-back instruction and data cache 256 K 8-way 2 nd level cache Intel IXP1200 32-bit RISC instruction set 1 strong ARM unit, 1 hash engine and 6 microengines Multithreading support for 4 threads for each microengine Maximum switching overhead of 1 cycle 128 32-bit GPRs in two banks of 64

13. Cross Comparisons

14. Summary Performance of two VLIW Processors, Trimedia TM1300 and TI TMS320C6701 were compared on IP routing application. Cross-comparison was made with the results of ARM SA-110, HPL-PD EPIC, and Intel IXP1200