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CS/CoE 536 : Lockwood 1 CS/CoE 536 Reconfigurable System On Chip Design Lecture 4 : Demonstration of Machine Problem 1 : CAM-based Firewall Washington.

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Presentation on theme: "CS/CoE 536 : Lockwood 1 CS/CoE 536 Reconfigurable System On Chip Design Lecture 4 : Demonstration of Machine Problem 1 : CAM-based Firewall Washington."— Presentation transcript:

1 CS/CoE 536 : Lockwood 1 CS/CoE 536 Reconfigurable System On Chip Design Lecture 4 : Demonstration of Machine Problem 1 : CAM-based Firewall Washington University Fall 2002 http://www.arl.wustl.edu/~lockwood/class/cs536/ Chris Neely, Chris Zuver Copyright 2002 Lockwood@arl.wustl.edu

2 CS/CoE 536 : Lockwood 2 MP1 Packet Classification Hardware CAM_MASK_2 CAM_VALUE_2 71033971 0 0 103 Src IP Dest IP Src Port Dest Port CAM_MASK_1 CAM_VALUE_1 0 0 103 Drop match <= ‘1’ when (input = 0xFFFFFFFFFFFFFFFFFFFFFFFFFF”) else ‘0’; Proto 0 840 72

3 CS/CoE 536 : Lockwood 3 Protocol Headers Cell Header IP Header UDP IP Header Payload PAD AAL5 Trailer AAL5 Frame Checksum AAL5 Frame LenCPS-UU & CPI AAL5 Pad

4 CS/CoE 536 : Lockwood 4 State Transitions for Processing Packet

5 CS/CoE 536 : Lockwood 5 Protocol Wrappers Timing Diagram DataEn SOF EOF Data SOC Data SOD AAIIIIIUUDDDDDDDDDDDDAA--PPPFF-- A-IIIIIUDDDDD----DDDDDDDFF----- A - I U U FP DATM HeaderIP Header Don't careFrame TrailerPadding Payload Data UDP Header CLK Cell Level Frame Level IP Level Only use these signals to process UDP/IP packets UDP payload starts 2 cycles after SOD signal. UDP payload ends with EOF signal. This cycle is optional. It does not appear in simulation Data Enabled during frame trailer

6 CS/CoE 536 : Lockwood 6 CAM Update Datagram Special UDP/IP Datagram updates values of CAM Entries –Allows software- controlled update of CAM registers –Fields alocated for: CAM_VALUE_1 CAM_MASK_1 CAM_VALUE_2 CAM_MASK_2 ATM Header Packet Len Source IP address 192.168.30.13 ( 0xC0A81E0D ) (Reserved) CAM_1_SRC_IP CAM_MASK_1 … (if necessary) ToSHLVer FragmentIP ID Src Port Dest Port ( 0x0320 ) LengthChecksum # CAMs AAL5 Pad CPS-UU & CPI AAL5 Frame Checksum Frame Len CAM_1_DEST_IP CAM_1_PORTS CAM_1_ PROTO (PAD) CAM_2_SRC_IP CAM_MASK_2 CAM_2_DEST_IP CAM_2_PORTS CAM_2_ PROTO (PAD) CAM_VALUE_1 CAM_MASK_1 CAM_VALUE_2 CAM_MASK_2 ChecksumProtoTTL

7 CS/CoE 536 : Lockwood 7 State Transitions for updating CAMs

8 CS/CoE 536 : Lockwood 8 FPX Hardware Design Flow Place and Route with constraints (Xilinx) Synthesize Logic to Xilinx gate technology (Synplicity) Verify Functionality (vsim) Test Module with actual traffic input Constrain Placement to FPX RAD Upload bitfile To FPX for testing Verify Post Place & Route Timing (ModelSim) Generate bitstream (Xilinx) Verify that that resulting packets have correct TTL Compile circuit (vcom)

9 CS/CoE 536 : Lockwood 9 Accessing FPGA Design Tools in Sever 201 Opening Cygwin, ModelSim, and Synplicity –Start Menu --> Engineering --> FPGA Tools

10 CS/CoE 536 : Lockwood 10 Downloading and extracting MP1 files Download the MP1 tar file from the website. Save the file under your CEC home directory (e.g. H:\class\cs536\MP1) Extract the files from Cygwin: –tar xvfz FireWall.tar.gz

11 CS/CoE 536 : Lockwood 11 Compiling the design Compiling the tools –cd sim –make compile Simulating the Design –make sim

12 CS/CoE 536 : Lockwood 12 ModelSim Simulation ModelSim Workspace Run simulation Open windows Select entity Select signals Force values View simulation waveforms

13 CS/CoE 536 : Lockwood 13 ModelSim Simulation [continued] Zooming in on waveforms Incoming packet Outgoing packet Zoom mode

14 CS/CoE 536 : Lockwood 14 ModelSim Simulation [continued] TTL Src IP Dest IP TTL <> 0 Src IP Transmitted Packet

15 CS/CoE 536 : Lockwood 15 ModelSim Simulation [continued] TTL Src IP Dest IP TTL = 0 Src IP Dropped Packet UPDATE SCREENSHOT!

16 CS/CoE 536 : Lockwood 16 Testbench Data Sample format of input data file (INPUT_CELLS.DAT) Compared to output data file (LC_CELLSOUT.DAT) Transmitted Packet Dropped Packet

17 CS/CoE 536 : Lockwood 17 Synthesizing the Design Synplicity Workspace

18 CS/CoE 536 : Lockwood 18 Synthesizing the Design [continued] Synplicity from the Cygwin console –make syn

19 CS/CoE 536 : Lockwood 19 Backend Tools : Generating the Bitstream Xilinx Tools

20 CS/CoE 536 : Lockwood 20 Testing the design on the FPX Screen shots of the upload

21 CS/CoE 536 : Lockwood 21 Testing the design on the FPX Screen shots of the upload

22 CS/CoE 536 : Lockwood 22 Testing the design on the FPX Screen shots of the upload

23 CS/CoE 536 : Lockwood 23 Testing the design on the FPX Screen shots of the upload

24 CS/CoE 536 : Lockwood 24 Testing the design on the FPX Screen shots of the upload

25 CS/CoE 536 : Lockwood 25 Testing the design on the FPX Screen shots of the upload

26 CS/CoE 536 : Lockwood 26 Verifying the Results Screenshots..

27 CS/CoE 536 : Lockwood 27 Creating the waveforms Creating waveforms…

28 CS/CoE 536 : Lockwood 28 Uploading your solutions Open the page –http://www.gradebot.com/cs536/submit/upload.cgi

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