1. CMOS Analog Design Using All-Region MOSFET Modeling 1 Chapter 2 Advanced MOS transistor modeling

2. CMOS Analog Design Using All-Region MOSFET Modeling 2 Semiconductors Four types of charge are present inside a semiconductor: the fixed positive charge of ionized donors, the fixed negative charge of ionized acceptors, the positive mobile charge of holes, and the negative mobile charge of electrons. We consider all donors and acceptors ionized On this basis, the net positive charge density ρ is

3. CMOS Analog Design Using All-Region MOSFET Modeling 3 Boltzmann’s Law – (1) In equilibrium electrons and holes follow Boltzmann’s law and their concentrations (number per unit volume) are proportional to k=1.38x10 -23 J/K - Boltzmann constant T - absolute temperature (K). electron and hole densities in equilibrium are related to electrostatic potential  by q=1.6x10 -19 C

4. CMOS Analog Design Using All-Region MOSFET Modeling 4 n 0 and p 0 - equilibrium electron and hole concentrations in the neutral bulk (  =0 ) - normalized electrostatic potential - thermal voltage the mass-action law is n i - concentration of electrons (and holes) in the intrinsic semiconductor Boltzmann’s Law – (2)

5. CMOS Analog Design Using All-Region MOSFET Modeling 5 Example: Calculate the built-in potential for a Si p-n junction with N A = 10 17 atoms/cm 3 and N D = 10 18 atoms/cm 3,T=300K In equilibrium, if we choose the potential origin  = 0 where the semiconductor is intrinsic (i.e., where p 0 =n 0 =n i ), then Far from the junction in the n-side Far from the junction in the p-side The built-in potential is given by

6. CMOS Analog Design Using All-Region MOSFET Modeling 6 The two-terminal MOS structure

7. CMOS Analog Design Using All-Region MOSFET Modeling 7 The ideal two-terminal MOS structure (V FB =0) A - capacitor area, t ox - oxide thickness  ox - permittivity of oxide M O S +s_+s_

8. CMOS Analog Design Using All-Region MOSFET Modeling 8 Example: oxide capacitance (a) Calculate the oxide capacitance per unit area for t ox = 5 and 20 nm assuming  ox = 3.9  0, where  0 = 8.85·10 -14 F/cm is the permittivity of free space. (b) Determine the area of a 1pF metal-oxide-metal capacitor for the two oxide thicknesses given in (a). Answer: (a) =690 nF/cm 2 = 6.9 fF/  m 2 for t ox =5 nm and = 172 nF/cm 2 = 1.7 fF/  m 2 for t ox = 20 nm. The capacitor areas are 145 and 580  m 2 for oxide thicknesses of 5 and 20 nm, respectively.

9. CMOS Analog Design Using All-Region MOSFET Modeling 9 The flat-band voltage In equilibrium (with the two terminals shortened/open), the contact potential between the gate and the semiconductor substrate of the MOS induces charges in the gate and the semiconductor for V GB =0. Charges inside the insulator and at the semiconductor-insulator interface also induce a semiconductor charge at zero bias. The effect of the contact potential and oxide charges can be counterbalanced by applying a gate-bulk voltage called the flat-band voltage V FB.

10. CMOS Analog Design Using All-Region MOSFET Modeling 10 Example: flat-band voltage (a) Determine the expression for the flat-band voltage of n + polysilicon-gate on p-type silicon (b) Calculate the flat-band voltage for an n + polysilicon-gate on p-type silicon structure with N A = 10 17 atoms/cm 3. Answer: (a) In equilibrium, by analogy with an n + p junction, the potential of the n + -region is positive with respect to that of the p- region. The flat-band condition is obtained by applying a negative potential to the n + gate with respect to the p-type semiconductor of value (b)

11. CMOS Analog Design Using All-Region MOSFET Modeling 11 Regions of operation of the MOSFET: Accumulation (p-substrate) Holes + accumulate in the p-type semiconductor surface + + + + + + + V GB G B - - - - - - - - - - - ++++ QoQo QGQG QCQC

12. CMOS Analog Design Using All-Region MOSFET Modeling 12 V GB G B + + + + + + + + + ++++ QoQo QGQG - - - - - - - - - QCQC - - - - -  F = Fermi potential ( to be defined) Holes evacuate from the P semiconductor surface and acceptor ion charges become uncovered - Regions of operation of the MOSFET: Depletion (p-substrate)

13. CMOS Analog Design Using All-Region MOSFET Modeling 13 V GB G B + + + + + + + + + ++++ QoQo QGQG - - - - - - - - - QCQC - - - - - - - - - - - - - - electrons approach the surface! Regions of operation of the MOSFET: Inversion (p-substrate)

14. CMOS Analog Design Using All-Region MOSFET Modeling 14 Inversion for p-type substrate Volume charge density inside the semiconductor: Depletion of holes prevails over electron charge when or, equivalently For  >  F the concentration of minority carriers (n) becomes higher than that of majority carriers (p); the semiconductor operates in the inversion region mass-action law

15. CMOS Analog Design Using All-Region MOSFET Modeling 15 Small-signal equivalent circuit of the MOS capacitor

16. CMOS Analog Design Using All-Region MOSFET Modeling 16 Main approximation for compact MOS modeling: the charge-sheet model Minority carriers occupy a zero-thickness layer at the Si-SiO 2 interface, where Charge-sheet + depletion approximation for the bulk charge gives is the body-effect coefficient

17. CMOS Analog Design Using All-Region MOSFET Modeling 17 The three-terminal MOS structure The origin of potential  is taken deep in the bulk n+ p VGVG VCVC Carrier concentrations in Si substrate follow Boltzmann’s law: n, p  exp(-Energy/kT) electrons are no longer in equilibrium with holes due to the bias of the source-bulk junction V C

18. CMOS Analog Design Using All-Region MOSFET Modeling 18 Approximations: 1)depletion capacitance per unit area is constant along the channel and is calculated neglecting inversion charge 2) Charge sheet model Small-signal equivalent circuit of the 3- terminal MOS device

19. CMOS Analog Design Using All-Region MOSFET Modeling 19 Determination of Potential balance The linearization surface potential  sa + _ + _

20. CMOS Analog Design Using All-Region MOSFET Modeling 20 Example: slope factor For t ox = 5 nm and 20 nm determine the minimum doping N A for which the slope factor n < 1.25 at  sa = 2  F. Answer: For  sa =2  F Thus, for n=1.25 where  F is a weak (logarithmic) function of N A. Using 2  F = 0.8 V for the first calculation, we obtain after two iterations that N A > 4.9x10 15 atoms/cm 3 for t ox =5nm, and N A > 2.3·10 14 atoms/cm 3 for t ox =20 nm.

21. CMOS Analog Design Using All-Region MOSFET Modeling 21 The Unified Charge Control Model (UCCM) - 1 Approximations: 1)depletion capacitance per unit area is constant along the channel and is calculated neglecting inversion charge 2) Charge sheet model

22. CMOS Analog Design Using All-Region MOSFET Modeling 22 The Unified Charge Control Model (UCCM) - 2 where Integrating from an arbitrary channel potential V C to a reference potential V P yields the unified charge control model (UCCM)

23. CMOS Analog Design Using All-Region MOSFET Modeling 23 The “regional” strong and weak inversion approximations or, equivalently strong inversion weak inversion

24. CMOS Analog Design Using All-Region MOSFET Modeling 24 Example : approximate UCCM (a)Calculate the value of the inversion charge density, normalized to, for which the value of the voltage V P -V S calculated using the SI approximation differs from that calculated using UCCM by 10 %; (b) Same using the WI approximation ; (c) comment on ‘moderate’ inversion (MI) Answer: a) SI approximation error of less than 10 % for q’ I > 20 b) WI approximation WI approximation error of less than 10 % for q’ I < 0.22. (c) MI region : SI and WI approximations give errors greater than 10 % for the control voltage V P -V S. The inversion charge density variation from the lower to the upper limit of the MI region is approximately two orders of magnitude (20/0.22).

25. CMOS Analog Design Using All-Region MOSFET Modeling 25 The pinch-off charge density The channel charge density corresponding to the effective channel capacitance times the thermal voltage, or thermal charge, defines pinch-off The name pinch-off is retained herein for historical reasons and means the channel potential corresponding to a small (but well-defined) amount of carriers in the channel.

26. CMOS Analog Design Using All-Region MOSFET Modeling 26 The pinch-off voltage V P The channel-to-substrate voltage (V C ) for which the channel charge density equals is called the pinch-off voltage V P. UCCM is asymptotically correct in weak inversion if in weak inversion

27. CMOS Analog Design Using All-Region MOSFET Modeling 27 Threshold voltage Equilibrium threshold voltage V T0, for V C =0: Gate voltage for which or Gate voltage for which V P =0 Recalling that it follows that

28. CMOS Analog Design Using All-Region MOSFET Modeling 28 Example: threshold voltage Estimate V T0 for an n-channel transistor with n + polysilicon gate, N A =10 17 atoms/cm 3 and t ox =5 nm. Answer: The flat-band voltage (slide 10) is -0.98 V;  F =0.419; C’ ox = 690 nF/cm 2. The body-effect factor is For this low value of the threshold voltage, the off-current (for V GS =0) is too high for digital circuits. Solution to control the magnitude of the threshold voltage without an exaggerated increase in the slope factor a non-uniform high-low channel doping.

29. CMOS Analog Design Using All-Region MOSFET Modeling 29 Pinch-off voltage vs. gate voltage Useful approximation: 4.0 3.0 2.0 1.0 0 0 1.0 2.0 3.0 4.0 5.0 2.0 1.5 1.0 0.5 0 V G (V) VPVP V T0 (equilibrium threshold voltage)

30. CMOS Analog Design Using All-Region MOSFET Modeling 30 The MOS transistor

31. CMOS Analog Design Using All-Region MOSFET Modeling 31 ‘Exact’ I-V model of the MOSFET (1) Using the Einstein relationship drift diffusion

32. CMOS Analog Design Using All-Region MOSFET Modeling 32 L is the channel length Since the current is constant along the channel ‘Exact’ I-V model of the MOSFET (2)

33. CMOS Analog Design Using All-Region MOSFET Modeling 33 + _ Charge-sheet formula for the current

34. CMOS Analog Design Using All-Region MOSFET Modeling 34 Charge control compact model (1) + _ + _ Integrating along the channel yields

35. CMOS Analog Design Using All-Region MOSFET Modeling 35 drift + diffusion average charge density average electric field “virtual” charge Charge control compact model (2)

36. CMOS Analog Design Using All-Region MOSFET Modeling 36 To emphasize the symmetry of the rectangular geometry MOSFET (compare with Ebers-Moll model of the BJT) Charge control compact model (3)

37. CMOS Analog Design Using All-Region MOSFET Modeling 37 Drain current vs. gate-to-bulk voltage

38. CMOS Analog Design Using All-Region MOSFET Modeling 38 Comparing UCCM and the surface potential model with exact numerical solution of Poisson equation

39. CMOS Analog Design Using All-Region MOSFET Modeling 39 Modeling the bulk charge from accumulation to inversion Charge-sheet approximation Potential balance

40. CMOS Analog Design Using All-Region MOSFET Modeling 40 Modeling from accumulation to inversion: Surface potential and pinch-off voltage (V P )

41. CMOS Analog Design Using All-Region MOSFET Modeling 41 Transistor symmetry Voltages referenced to local substrate: V G  V GB V S  V SB V D  V DB VGVG VDVD VSVS B IDID 1. 2. Symmetry VGVG V2V2 V1V1 B IDID

42. CMOS Analog Design Using All-Region MOSFET Modeling 42 3. For a long-channel MOSFET I S and I SQ are the normalization (specific) current and the “sheet” normalization current, slightly dependent on bias. Normalization D S B IDID G

43. CMOS Analog Design Using All-Region MOSFET Modeling 43 Long-channel MOSFET I F : forward current I R : reverse current IF=IF= IR=IR= Forward and reverse currents

44. CMOS Analog Design Using All-Region MOSFET Modeling 44 The specific (normalization) current I SQ : process parameter slightly dependent on V G and T I SQ  25 nA (p-channel) I SQ  75 nA (n-channel) in 0.35  m CMOS Specific current

45. CMOS Analog Design Using All-Region MOSFET Modeling 45 UCCM & V T0 VPVP VGVG Slope =1 Slope =1/n V G0 V P0 Linearization: In particular: Pinch-off voltage and slope factor (1)

46. CMOS Analog Design Using All-Region MOSFET Modeling 46 Determination of the pinch-off voltage and the slope factor as functions of V G. NMOS transistor W=20  m, L=2  m, 0.18  m CMOS technology. Pinch-off voltage and slope factor (2)

47. CMOS Analog Design Using All-Region MOSFET Modeling 47 Common-source characteristics 10 -3 10 -6 10 -9 V S = 0 V 3.0 2.5 2.0 1.5 0.5 1.0 0 1 2 3 4 V G (V) I D (A) V D = V G VDVD IDID VGVG VSVS The I-V relationship (1)

48. CMOS Analog Design Using All-Region MOSFET Modeling 48 V G = 4.8 V I D (A) V D = V G 10 -3 10 -6 10 -9 0 1 2 3 V S (V) 0.8 V Common-gate characteristics V G =0.8, 1.2, 1.6, 2.0, 2.4, 3.0, 3.6, 4.2, and 4.8 V VDVD IDID VSVS VGVG The I-V relationship (2)

49. CMOS Analog Design Using All-Region MOSFET Modeling 49 Weak inversion i f(r) <1 i f(r) /2 Weak inversion model

50. CMOS Analog Design Using All-Region MOSFET Modeling 50 Strong inversion i f(r) >>1 Moderate inversion 1<i f(r) <100 Both sqrt(.) and ln(.) terms are important Strong inversion model (1)

51. CMOS Analog Design Using All-Region MOSFET Modeling 51 I D /I F 1 V DSsat =V P =(V G -V T0 )/nV DS IDID VGVG Transistor output characteristic Strong inversion model (2)

52. CMOS Analog Design Using All-Region MOSFET Modeling 52 V DD IDID VGVG VGVG V T0 SCE, , n, “model” VSVS V DD IDID VSVS VGVG Strong inversion model (3)

53. CMOS Analog Design Using All-Region MOSFET Modeling 53 (a) i f = 4.5x 10 -2 (V G =0.7 V); (b) i f = 65(V G = 1.2 V); (c) i f = 9.5x10 2 (V G = 2.0 V); (d) i f = 3.1x 10 3 (V G = 2.8 V); (e) i f = 6.8x 10 3 (V G = 3.6 V); (f) i f = 1.2x 10 4 (V G = 4.4 V). Universal output characteristics (o): measured (—): model

54. CMOS Analog Design Using All-Region MOSFET Modeling 54 Saturation voltage ( V DSsat ) – V DS such that is the saturation level Saturation voltage

55. CMOS Analog Design Using All-Region MOSFET Modeling 55 Transconductances Calculation of g ms Pao-Sah I D (UCCM) UCCM in saturation Transconductances - 1

56. CMOS Analog Design Using All-Region MOSFET Modeling 56 Source transconductance V G = 0.8, 1.2, 1.6, 2.0, 2.4, 3.0, 3.6, 4.2, and 4.8 V (W=L=25  m, tox=280 Å) V DD IDID VSVS VGVG Transconductances - 2

57. CMOS Analog Design Using All-Region MOSFET Modeling 57 Gate transconductance V S = 0, 0.5, 1.0,1.5, 2.0, 2.5, and 3.0 V. W=L=25  m, tox=280 Å V DD IDID VGVG VSVS Transconductances - 3

58. CMOS Analog Design Using All-Region MOSFET Modeling 58 Transconductance -to-current ratio WI ( i f <1) SI ( i f >>1) W=25  m L=25  m, t ox = 280 Å L=20  m, t ox = 55 Å The transconductance-to-current ratio - 1

59. CMOS Analog Design Using All-Region MOSFET Modeling 59 Transconductance -to-current ratio WI ( i f <1) SI ( i f >>1) W=L=25  m, t ox = 280 Å 10 -4 10 -2 10 0 10 2 10 4 V GB = 2.0 V (I S = 26 nA) V GB = 1.0 V (I S = 33 nA) V GB = 3.0 V (I S = 24 nA) model ifif 10 2 10 1 10 0 g ms /I F The transconductance-to-current ratio - 2

60. CMOS Analog Design Using All-Region MOSFET Modeling 60 Transconductance -to-current ratio WI ( i f <1) SI ( i f >>1) W=25  m, t ox = 280 Å L = 25  m (I S = 26 nA) model 10 -4 10 -2 10 0 10 2 10 4 ifif 10 2 10 1 10 0 g ms /I F L = 2.5  m (I S = 260 nA) The transconductance-to-current ratio - 3

61. CMOS Analog Design Using All-Region MOSFET Modeling 61 G B S D idid The low-frequency small-signal model

62. CMOS Analog Design Using All-Region MOSFET Modeling 62 Quasi-static charge-conserving model The current entering each terminal of the transistor is split into a transport component (I T ) and a capacitive charging term. Quasi-static approximation: To calculate the stored charges we suppose that the charge stored in the transistor depends only on the instantaneous terminal voltages Neglecting leakage currents

63. CMOS Analog Design Using All-Region MOSFET Modeling 63 Ward-Dutton partition of the channel charge As expected is the total inversion charge stored in the channel

64. CMOS Analog Design Using All-Region MOSFET Modeling 64 Calculation of stored charge - 1 It is convenient to define

65. CMOS Analog Design Using All-Region MOSFET Modeling 65 In weak inversion In strong inversion & saturation or Using we find that Calculation of stored charge - 2

66. CMOS Analog Design Using All-Region MOSFET Modeling 66 Total inversion, source and drain charges Channel linearity coefficient =1 in WI =1 in SI for V DS =0  0 in SI sat

67. CMOS Analog Design Using All-Region MOSFET Modeling 67 Capacitive coefficients - 1 Using the quasi-static approximation Defining

68. CMOS Analog Design Using All-Region MOSFET Modeling 68 The 16 capacitive coefficients are not linearly independent Assume Under equal terminal voltage variations, the charging currents are zero. For the gate charging current, e.g., we have Similarly, for S, D, and B nodes Capacitive coefficients - 2

69. CMOS Analog Design Using All-Region MOSFET Modeling 69 Assume that The sum of all the charging currents is Charge conservation, d(Q S +Q D +Q B +Q G )/dt=0 Capacitive coefficients - 3

70. CMOS Analog Design Using All-Region MOSFET Modeling 70 Linear relationships between capacitive coefficients Only nine out of the sixteen capacitive coefficients are linearly independent Capacitive coefficients - 4

71. CMOS Analog Design Using All-Region MOSFET Modeling 71 A complete set of 9 capacitive coefficients for the MOSFET

72. CMOS Analog Design Using All-Region MOSFET Modeling 72 Simplified small-signal MOSFET model G D S B C gs C bs CgdCgd C bd C gb

73. CMOS Analog Design Using All-Region MOSFET Modeling 73 The five capacitances of the simplified model Intrinsic capacitances simulated from (___) the charge-based and (o) from the  S - model (NMOS transistor, t ox = 250Å, N A =2x10 16 cm -3, and V T0 =0.7V.

74. CMOS Analog Design Using All-Region MOSFET Modeling 74 Capacitances of extrinsic transistor - 1

75. CMOS Analog Design Using All-Region MOSFET Modeling 75 Capacitances of extrinsic transistor - 2

76. CMOS Analog Design Using All-Region MOSFET Modeling 76 Non-quasi-static (NQS) small-signal model Channel segmentation: representation of the MOSFET as a series combination of short transistors

77. CMOS Analog Design Using All-Region MOSFET Modeling 77 Simplified high-frequency MOSFET model G D S B

78. CMOS Analog Design Using All-Region MOSFET Modeling 78 Time constants of the NQS MOSFET model

79. CMOS Analog Design Using All-Region MOSFET Modeling 79 Quasi-static small-signal model  1 <<1  2(3) <<1 non-quasi-static model reduces to the five-capacitor model B G D S

80. CMOS Analog Design Using All-Region MOSFET Modeling 80 Calculate I D, V DSsat and small-signal parameters of a saturated n- channel MOSFET in 0.35  m technology at i f = 3 with V SB = 0. W=10  m, L=1  m, t ox =7 nm, n=1.2,  n =400 cm 2 /V-s at 300 K. Answer: =493 nF/cm 2 and = 80 nA. g md = 0, C gd = 0 and C bd = 0 since the transistor is saturated. Example: Small-signal parameters

81. CMOS Analog Design Using All-Region MOSFET Modeling 81  =1/(1+1)=0.5 Example: Small-signal parameters (continued)

82. CMOS Analog Design Using All-Region MOSFET Modeling 82 Intrinsic transition frequency

83. CMOS Analog Design Using All-Region MOSFET Modeling 83 Determine the inversion level for which the transition frequency of a minimum (nominal) length NMOS transistor in the 0.35  m technology is 10 GHz at room Answer: Assuming that n=1.2 and  n = 400 cm 2 /V-s at 300 K it follows that Thus, operation in moderate inversion can be considered for a design at 1 GHz, for example. Example: Transition frequency

84. CMOS Analog Design Using All-Region MOSFET Modeling 84 Main short-channel effects Mobility dependence on the electric field Channel length modulation Drain-induced barrier lowering Velocity saturation

85. CMOS Analog Design Using All-Region MOSFET Modeling 85 Mobility dependence on the electric field Inclusion of mobility variations in compact modeling: the constant mobility is substituted with an effective mobility, which depends on the applied voltages.  0, the low-field mobility and  , the scattering constant, are fitting parameters Another simplification: the effective transversal field is assumed constant along the channel and equal to its value at pinch-off.

86. CMOS Analog Design Using All-Region MOSFET Modeling 86 Channel length modulation The dependence of the effective channel length on the drain-to-source voltage is referred to as the channel length modulation (CLM). y S 0 IDID V DSsat LeLe L V DS LL D

87. CMOS Analog Design Using All-Region MOSFET Modeling 87 Drain-induced barrier lowering (DIBL) An increase in the drain voltage produces an increase in the surface potential in the channel and, consequently, a reduction in the potential barrier seen by the electrons at the source ( DIBL). The inclusion of the DIBL effect in MOSFET models is generally through the threshold voltage.

88. CMOS Analog Design Using All-Region MOSFET Modeling 88 (longitudinal field) v sat v F ss FCFC Velocity saturation effects - 1 Allows analytical integration for I D

89. CMOS Analog Design Using All-Region MOSFET Modeling 89 Velocity saturation effects - 2

90. CMOS Analog Design Using All-Region MOSFET Modeling 90 Velocity saturation effects - 3 Normalized current vs. normalized charge densities Normalization (specific) current : ratio of diffusion-related velocity to saturation velocity short-channel short-channel parameter

91. CMOS Analog Design Using All-Region MOSFET Modeling 91 0 S D IDID V DS Saturation: The minimum amount of electron charge flowing at the saturation velocity, required to sustain the current is Velocity saturation effects - 4

92. CMOS Analog Design Using All-Region MOSFET Modeling 92 Velocity saturation effects - 5 10 -2 10 0 10 2 10 4 1 weak inversion strong inversion Short channel Long channel

93. CMOS Analog Design Using All-Region MOSFET Modeling 93 Small dimension effects on charges and capacitances

94. CMOS Analog Design Using All-Region MOSFET Modeling 94 Virtual inversion charge density inversion +pinch off -saturation charge densities Along the channel Virtual charge formalism - 1

95. CMOS Analog Design Using All-Region MOSFET Modeling 95CMOS Analog Design Using All Region MOSFET Modeling 95 The drift of the virtual charge produces the same current as the actual movement of the real charge, which includes drift, diffusion and velocity saturation Virtual charge formalism -2

96. CMOS Analog Design Using All-Region MOSFET Modeling 96 Channel linearity coefficient  with v sat The integration of from source to drain results in where

97. CMOS Analog Design Using All-Region MOSFET Modeling 97 Stored charges including v sat The stored charge is calculated changing the integration variable from y to resulting in

98. CMOS Analog Design Using All-Region MOSFET Modeling 98 Source and drain charges including v sat

99. CMOS Analog Design Using All-Region MOSFET Modeling 99 Capacitive coefficients including v sat - 1

100. CMOS Analog Design Using All-Region MOSFET Modeling 100 Normalized capacitances versus drain-source voltage Capacitive coefficients including v sat - 1

101. CMOS Analog Design Using All-Region MOSFET Modeling 101 Gate-to-bulk capacitance with and without the effect of velocity saturation