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Trends in Front-End ASICs for Particle Physics
Gianluigi De Geronimo Brookhaven National Laboratory , +1(631) TIPP - Amsterdam - June 2014
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Outline CMOS Technologies ASICs for Particle Physics Challenges and Paradigm
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Microelectronics Art of combining micrometer-scale components into a single monolithic device: Integrated Circuit (IC) ~ 20,000 µm ~ 20 µm D G The most widely adopted IC technologies use the MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor S L
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The Rapid Evolution of Microelectronics
~ every 20 years ~ 202 every 20 years
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From Planar FET to FinFET (3D FET)
Conducting channels on three sides of a vertical "fin" structure, providing "fully depleted" operation - introduced in late '90s Combine 20nm-Planar FETs and sub-20nm FinFETs 55% drop in power dissipation or 35% boost in speed compared to 28nm-Planar
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The Rapid Evolution of Microelectronics
Exotic Transistors single-electron carbon-nanotube ... ~ every 20 years ~ 202 every 20 years Introduced in the ’90s, exotic transistors made considerable progress, but are still far from achieving reproducibility and reliability required by microelectronics
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High-Density Interconnects - 2.5D and 3D
· Through-Silicon Via (TSV) vertical interconnects through active or passive die - µm diameter · Micro-Bump / Metal-Metal Bonds 2D interconnects - µm size 2.5D TSV active dies passive Si interposer with planar and vertical (TSV) interconnects micro-bumps active die active dies with TSVs flip-chip bumps stack many dies with different functionalities micro-bumps 3D TSV
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The Rapid Evolution of Microelectronics
TSV Exotic Transistors single-electron carbon-nanotube ... ~ every 20 years ~ 202 every 20 years ?! Progress heavily driven by consumer electronics
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PP has little chance to make an impact on evolution
Semiconductor Market Billion Dollars PP 50M? Year PP has little chance to make an impact on evolution
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Microelectronics and Particle Physics Radiation Detectors ?
data processing and computing, communication, ... Radiation Detectors ? front-end instruments - the “eye” of the scientist Require custom-designed front-end electronics frequently in the form of Application-Specific Integrated Circuits optimized front-end circuit small physical size low power dissipation radiation tolerance cost (in context of whole detector) ... Front-end ASIC
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AMPLEX (1988) - First Large Scale
16 channels, ~800 MOSFETs (~50/ch) 3µm CMOS, 5V, 1.1 mW/ch, 16 mm² amplifier/filter/track & hold/mux for Silicon micro-strips at UA2
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specialized working groups
FE-I5 ( ?) 260k pixels, 1G MOSFETs (~4,000/px) 65nm, 1.2V, W/cm², >400mm² high complexity/functionality, DSP for ATLAS vertex hybrid pixels 19 institutions specialized working groups 100 collaborators (~50 ASIC designers) 2X2 pixel unit ARCHITECTURE
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Compare to Evolution of Microelectronics
Delay from characterization, prototyping prices, resources
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VMM (2015-16?) 64 channels, >6M MOSFETs (>80k/ch)
130nm, 1.2V, 0.4 W/cm², >110mm² high complexity/functionality w/DSP for ATLAS muon spectrometer/tracker V. Polychronakos New Small Wheels sTGC , MicroMegas, 2.3M channels
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Impact on ATLAS New Small Wheels
ASM VMM 60x sensing elements (32k→2M), 10x element density (5→0.5 mm) 3x power dissipation (300→15 mW/element) comparable data-transfer bandwidth, fully data-driven, discrimination trigger primitives, timing measurements, programmable polarity (1) FE ASICs will become very-high-complexity systems-on-chip (SOC) and will require high-density interconnects
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Front-end ASICs vs Year sources: HEPIC 2014 White Paper et al.
2013 ~ 60 FE (out of ~140) ~ 35 FE in design sources: HEPIC 2014 White Paper et al. (2) The demand for FE ASICs is increasing
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Front-End ASICs vs Technology
complexity availability prices resources (3) PP ASICs are keeping pace with technology
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The PP-ASIC Paradigm Advances in Particle Physics detectors are tightly coupled to advances in ASICs and associated interconnects
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Design Groups – Current Status
active designs ≈ 30-40 Average one design per group institutions leading collaborative efforts institutions performing R&D on technologies One FE-ASIC design currently requires 2-4 full-time designers and 2-4 years average, from concept to ready-for-production
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Design Groups – Current Status
In order to be efficient and maintain state-of-the-art ASIC groups must: develop 1-2 new designs and 2-4 revisions per year work with 2 technologies (re-usage & next) perform R&D on circuits and technologies The critical minimum is currently 5-6 designers Need to diversify while contributing to PP with an average of % of resources PP currently supports/uses up to %
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The number of ASIC designers has to increase !
The PP-ASIC Paradigm Collaborations ? only part of the solution communication overhead lead of large group The number of ASIC designers has to increase ! involve non-PP ASIC groups increase size of PP ASIC groups
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Evolution of Front-End ASIC Design Groups
In order to contribute to future PP detectors FE ASIC groups need to: grow (30-40%) increase collaborations (know-how exchange) develop/acquire "system-level FE ASIC designer" develop/acquire "high-density interconnects“ align technologies evolve and coordinate R&D PP community needs to contribute with 25-30% Alternative? Pay companies (hundreds M$)
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Aligning Technologies skip technologies ... ~ jointly
Long-lasting choice (re-usage) Collaborations (know-how) skip technologies ... ~ jointly Specialized groups must perform characterization Initial phase of pioneering projects (large groups) Some exceptions for specialized technologies
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Coordinating R&D R&D on enabling circuits/technologies low-power ADCs
low-power DSP (auto-calib., data red., program., ...) low-power high-speed communication (standards) low-power low-voltage analogs high dynamic range, waveform sampling high-density interconnects (2.5D, 3D - incl. sensors) cryogenic MAPS ... keep < 1W/cm² When to exit/enter a technology ? exit too late may result in limited collaborations enter too early may result in waste of resources
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Conclusions Advances in PP detectors are tightly coupled to advances in front-end ASICs and associated interconnects Front-end ASICs: dramatic increase in complexity/functionality (SOC) increase in demand need to keep pace with the technologies ASIC groups: increase size and collaborations (know-how) perform R&D towards SOC and interconnects align technologies and coordinate R&D Acknowledgment G. C. Smith, V. Radeka, BNL Microelectronics, CERN, PP FE ASIC Community
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IC Designer in a “Collaboration”
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Prototyping costs are increasing (price, size)
Prototyping Prices prices 1/2 every ~5 years Prototyping costs are increasing (price, size)
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