1. George Mason University ECE 448 – FPGA and ASIC Design with VHDL Lecture 18 FPGA Boards & FPGA-based Supercomputers High Level Language (HLL) Design Methodology

2. 2ECE 448 – FPGA and ASIC Design with VHDL Resources PCI http://en.wikipedia.org/wiki/Peripheral_Component_Interconnect PCI-X http://en.wikipedia.org/wiki/PCI-X Reconfigurable Supercomputing T. El-Ghazawi, K. Gaj, D. Buell, D. Pointer Tutorial at the Supercomputing 2005 conference http://hpcl.seas.gwu.edu/openfpga/tutorial_html/index.html

3. 3ECE 448 – FPGA and ASIC Design with VHDL FPGA Device Capacity Trends Year 1985 Xilinx Device Complexity XC2000 50 MHz 1K gates XC4000 100 MHz 250K gates Virtex 200 MHz 1M gates Virtex-II 450 MHz 8M gates Spartan 80 MHz 40K gates Spartan-II 200 MHz 200K gates Spartan-3 326 MHz 5M gates 19911987 XC3000 85 MHz 7.5K gates Virtex-E 240 MHz 4M gates XC5200 50 MHz 23K gates 199519981999200020022003 Virtex-II Pro 450 MHz 8M gates* 20042006 Virtex-4 500 MHz 16M gates* Virtex-5 550 MHz 24M gates* Source: http://class.ece.iastate.edu/cpre583/lectures/Lect-01.ppt

4. George Mason University ECE 448 – FPGA and ASIC Design with VHDL FPGA Boards

5. 5ECE 448 – FPGA and ASIC Design with VHDL General Architecture of an FPGA-Based Board BUS Processing Element (PE#0) Processing Element (PE#1) Processing Element (PE#N-1) COMMON MEMORY / INTERCONNECT NETWORK LOCAL MEMORY LOCAL MEMORY LOCAL MEMORY CLK BUS INTERFACE CONTROLLER I/O CARD

6. 6ECE 448 – FPGA and ASIC Design with VHDL Reconfigurable Computing Boards Boards may have one or several interconnected FPGA chips Support different bus standards, e.g. PCI, PCI-X, USB, etc. May have direct real-time data I/O through a daughter board Boards may have local onboard memory (OBM) to handle large data while avoiding the system bus (e.g. PCI) bottleneck

7. 7ECE 448 – FPGA and ASIC Design with VHDL Many boards per node can be supported Host program (e.g. C) to interface user (and  P) with board via a board API Driver API functions may include functionalities such as Reset, Open, Close, Set Clocks, DMA, Read, Write, Download Configurations, Interrupt, Readback Reconfigurable Computing Boards

8. 8ECE 448 – FPGA and ASIC Design with VHDL Common Interface - PCI PCI = Peripheral Component Interconnect 32-bit bus 64-bit bus

9. 9ECE 448 – FPGA and ASIC Design with VHDL PCI - Conventional hardware specifications 32-bit or 64-bit bus width 33.33 MHz clock with synchronous transfers peak transfer rate of 133 MB per second for 32-bit bus width (33.33 MHz × 32 bits × (1 byte ÷ 8 bits) = 133 MB/s) peak transfer rate of 266MB/s for 64-bit bus width 32-bit address space (4 gigabytes) 32-bit port space 5-volt signaling

10. 10ECE 448 – FPGA and ASIC Design with VHDL PCI-X (PCI eXtended) PCI-X doubles the width to 64-bit, revises the protocol, and increases the maximum signaling frequency to 133 MHz (peak transfer rate of 1014 MB/s) PCI-X 2.0 permits a 266 MHz rate (peak transfer rate of 2035 MB/s) and also 533 MHz rate, adds a 16-bit bus variant and allows for 1.5 volt signaling

11. 11ECE 448 – FPGA and ASIC Design with VHDL Some Reconfigurable Boards Vendors ANNAPOLIS MICRO SYSTEMS, INC. (www.annapmicro.com) University of Southern California -USC/ISI (http://www.east.isi.edu). AMONTEC (www.amontec.com/chameleon.shtml) XESS Corporation (www.xess.com) CELOXICA (www.celoxica.com) CESYS (www.cesys.com) TRAQUAIR (www.traquair.com) SILICON SOFTWARE: (www.silicon-software.com) COMPAQ: (www.research.compaq.com/SRC/pamette/) ALPHA DATA: (www.alpha-data.com) Associated Professional Systems: (www.associatedpro.com) NALLATECH: (www.nallatech.com)

12. 12ECE 448 – FPGA and ASIC Design with VHDL WILDSTAR™ II Pro Reproduced and displayed with permission

13. 13ECE 448 – FPGA and ASIC Design with VHDL WILDSTAR™ II Pro Reproduced and displayed with permission

14. George Mason University ECE 448 – FPGA and ASIC Design with VHDL Reconfigurable Supercomputers

15. 15ECE 448 – FPGA and ASIC Design with VHDL Scalable Reconfigurable Systems Large numbers of reconfigurable processors and microprocessors Everything can be configured Functional units Interconnects Interfaces High-level of scalability Suitable for a wide range of applications Everything can be reconfigured over and over at run time (Run-Time Reconfiguration) to suite underlying applications Can be easily programmed by application scientists, at least in the same way of programming conventional parallel computers

16. 16ECE 448 – FPGA and ASIC Design with VHDL Interface  P memory  P memory... PP PP I/O Interface FPGA memory FPGA memory... FPGA... I/O Microprocessor systemReconfigurable system Early Reconfigurable Architecture

17. 17ECE 448 – FPGA and ASIC Design with VHDL Current Reconfigurable Architecture... Shared Memory and or NIC FPGA memory FPGA  P memory PP FPGA memory FPGA  P memory PP

18. 18ECE 448 – FPGA and ASIC Design with VHDL Possible Classes of Reconfigurable Supercomputers μP BoardRP Board … μP 1μP N … RP 1RP N Joint μP/RP Board … μP 1μP N … RP 1RP N Tighter Integration Independent Board Design Joint Board Design

19. 19ECE 448 – FPGA and ASIC Design with VHDL Possible Classes of Reconfigurable Supercomputers – cont. Tighter Integration μP inside of RP Design RP inside of μP Design Joint μP/RP Board μP 1 … RP 1 μP N RP N Joint μP/RP Board RP 1 … μP 1 RP N μP N

20. 20ECE 448 – FPGA and ASIC Design with VHDL FPGA based supercomputers Machine Released SRC 6 from SRC Computers Cray XD1 from from Cray SGI Altix from SGI SRC 7 from SRC Computers, Inc, 2002 2005 2006

21. 21ECE 448 – FPGA and ASIC Design with VHDL How to choose the system that best suits your needs? Typical users’ criteria: 1. Clock speed 2. Amount of memory 3. Cost of Ownership

22. 22ECE 448 – FPGA and ASIC Design with VHDL How to choose the system that best suits your needs? Recommended users’ criteria: 1.Tools - right level of abstraction - ease of development & verification - progress & backward compatibility 2. Libraries - basic operations - examples of full applications 3. Technical support

23. 23ECE 448 – FPGA and ASIC Design with VHDL How to choose the system that best suits your needs? Recommended users’ criteria (cont.): 4. Data Bandwidth Reconfigurable Processor System  P system external I/O devices

24. 24ECE 448 – FPGA and ASIC Design with VHDL How to choose the system that best suits your needs? Recommended users’ criteria (cont.): 5. Scalability - variable power and price - efficient communication among the modules

25. 25ECE 448 – FPGA and ASIC Design with VHDL Recommended users’ criteria (cont.): 6. Transfer of control overhead Theoretical behavior Actual behavior PP FPGA time PP FPGA Control transfer overhead

26. George Mason University ECE 448 – FPGA and ASIC Design with VHDL High Level Language (HLL) Design Methodology Handel C

27. 27ECE 448 – FPGA and ASIC Design with VHDL Behavioral Synthesis Algorithm I/O Behavior Target Library Behavioral Synthesis RTL Design Logic Synthesis Gate level Netlist Classic RTL Design Flow

28. 28ECE 448 – FPGA and ASIC Design with VHDL Need for High-Level Design Higher level of abstraction Modeling complex designs Reduce design efforts Fast turnaround time Technology independence Ease of HW/SW partitioning

29. 29ECE 448 – FPGA and ASIC Design with VHDL Advantages of Behavioral Synthesis Easy to model higher level of complexities Smaller in size source compared to RTL code Generates RTL much faster than manual method Multi-cycle functionality Loops Memory Access

30. 30ECE 448 – FPGA and ASIC Design with VHDL High-Level Languages C/C++-Based Handel C – Celoxica Ltd., UK Impulse C – Impulse Accelerated Technologies Catapult C – Impulse Accelerated Technologies System C – The Open SystemC Initiative Java-based Forge – Xilinx JHDL – Brigham Young University

31. 31ECE 448 – FPGA and ASIC Design with VHDL Other High-Level Design Flows Matlab-based System Generator for DSP – Xilinx AccelChip DSP Synthesis – AccelChip GUI Data-Flow based Corefire – Annapolis Microsystems RC Toolbox – DSPlogic

32. 32ECE 448 – FPGA and ASIC Design with VHDL Handel C Design Flow

33. 33ECE 448 – FPGA and ASIC Design with VHDL Design Flow Executable Specification Handel-C Synthesis Place & Route VHDL EDIF

34. 34ECE 448 – FPGA and ASIC Design with VHDL Handel-C/ANSI-C Comparisons Preprocessors i.e. #define Structures ANSI-C Constructs for, while, if, switch Functions Arrays Pointers Arithmetic operators Bitwise logical operators Logical operators ANSI-C Standard Library Side Effects i.e. X = Y++ Recursion Floating Point Handel-C Standard Library Parallelism Arbitrary width variables RAM, ROM Signals Channels Interfaces Enhanced bit manipulation ANSI-CHANDEL-C

35. 35ECE 448 – FPGA and ASIC Design with VHDL Variables Only one fundamental type for variables: int int 5 x; unsigned int 13 y; Default types char8 bits short16 bits long 32 bits

36. 36ECE 448 – FPGA and ASIC Design with VHDL Type Summary TypeWidth char8 bits unsigned char8 bits short16 bits unsigned short16 bits long32 bits unsigned long32 bits intCompiler unsigned intCompiler int nn bits unsigned int nn bits unsigned nn bits

37. 37ECE 448 – FPGA and ASIC Design with VHDL Arrays Same way as in ANSI-C int 6 x[7]; 7 registers of 6 bits wide unsigned int 6 x [4] [5] [6]; 120 registers of 6 bits wide Index must be a compile time constant. If random access is required, consider using RAM or ROM

38. 38ECE 448 – FPGA and ASIC Design with VHDL Internal RAMs and ROMs Using ram and rom keywords ram int 6 a [43]; a RAM consisting of 43 entries of 6 bits wide rom int 16 b [4]; a ROM consisting of 4 entries of 16 bits wide RAMs and ROMs are accessed the same way that arrays are accessed in ANSI-C Index need not be a compile time constant

39. 39ECE 448 – FPGA and ASIC Design with VHDL Restrictions on RAMs and ROMs RAMs and ROMs are restricted to performing operations sequentially. Only one element may be addressed in any given clock cycle ram unsigned int 8 x [4]; x [1] = x [3] + 1;illegal if (x [0] == 0) x [1] = 1;illegal

40. 40ECE 448 – FPGA and ASIC Design with VHDL Multi-port RAMs static mpram Fred { ram ReadWrite[256]; (read/write port) rom Read[256]; (read only port) } Now we can read and write in a given clock cycle

41. 41ECE 448 – FPGA and ASIC Design with VHDL Dual Port Memory

42. 42ECE 448 – FPGA and ASIC Design with VHDL Handel-C Language (1) A subset of ANSI-C Sequential software style with a “par” construct to implement parallelism A channel “chan” statement allows for communication and synchronization between parallel branches Level of design abstraction is above RTL but below behavioral

43. 43ECE 448 – FPGA and ASIC Design with VHDL Handel-C Language (2) Each assignment and delay statement take one clock cycle Automatic generation of the state machine from an algorithmic description of the circuit in terms of parallel and sequential blocks Automatic scheduling of parallel and sequential blocks, that is the code following a group is scheduled only after that whole group has completed

44. 44ECE 448 – FPGA and ASIC Design with VHDL Parallelism Parallel blocks Statement

45. 45ECE 448 – FPGA and ASIC Design with VHDL Par construct - Examples

46. 46ECE 448 – FPGA and ASIC Design with VHDL Par constructs - timing

47. 47ECE 448 – FPGA and ASIC Design with VHDL Par construct – shift register

48. 48ECE 448 – FPGA and ASIC Design with VHDL Handel C vs. C - functions Functions may not be called recursively, since all logic must be expanded at compile-time to generate hardware You can only call functions in expression statements. These statements must not contain any other calls or assignments. Variable length parameter lists are not supported. Old-style ANSI-C function declarations (where the type of the parameters is not specified) are not supported. main() functions take no arguments and return no values. Each main() function is associated with a clock. If you have more than one main() function in the same source file, they must all use the same clock.

49. 49ECE 448 – FPGA and ASIC Design with VHDL Handel-C Overview High-level language based on ISO/ANSI-C for the implementation of algorithms in hardware Allows software engineers to design hardware without retraining Clean extensions for hardware design including flexible data widths, parallelism and communications Based on Communicating Sequential Process model Independent parallel processes “par” construct to specify parallel computation blocks within a process Well defined timing model Each statement takes a single clock cycle Includes extended operators for bit manipulation, and high-level mathematical macros (including floating point)