1. 1 Abstract & Main Goal המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory The focus of this project was the creation of an analyzing device for a std. PCI-Express (1.0) communication line at speeds of 2.5Gb/sec. by means of a VHDL core on a Xilinx “Virtex II pro” FPGA platform. The core implements Real Time Hardware based algorithms and enables the user to monitor and analyze PCI-Express transactions using a simple register based interface.

2. 2 Architecture Development המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory ISA Parallel PCI Parallel Signaling Rate [Ghz] 1980’s1990’s2000’s ~ ~ 1 5 10 15 Parallel Bus limit PCI-Express 3 rd Generation I/O Serial Protocol

3. 3 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Vs Classic PCI End point Legacy End point Switch CPU Root Complex PCI Express GFX PCI Bridge PCI Legacy End point End point Memory Switched Fabric Arch PCI-X Device PCI-X Device CPU Host Bridge AGP GFX PCI Bridge PCI PCI-X Bridge PCI Bridge PCI-X Bridge PCI-X Device PCI-X Device Memory BUS Arch

4. 4 PCI-Express - Architecture המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Dual Simplex Differential 2.5 Gbps/direction Separate clock ! x1 Lane Wide Link Switch Operation Traffic Direction End Point

5. 5 PCI-Express - Protocol המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Split Transaction - Request/Complete Memory I/O Configuration Message Transaction Data Link Physical 3 Layers

6. 6 R&D – Signal Integrity System Under Test Digital signal requirements : Complete and Unimpaired Accurate placement in time Stable, valid logic levels Clean, fast transitions Transient free המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Analyzers offer a vital validation Tool !

7. 7 R&D – Data Integrity System Under Test Data Packets requirements : Complete & Unimpaired Protocol Compliant Valid structures Valid symbols Error free המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Data Integrity is the main focus of this project !

8. 8 Analyzers - Market Survey Algorithms – Software manifested Offline filtering - Storage Limit Stand alone Tool No open source High Cost – 30,000 $ המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

9. 9 Project Goals Standard Hardware – Low Cost Low Storage Demand PCIe (1.0) Compliant Bit Level Filtering Control Simple User Friendly Interface Educational Merits – Lab Experiment המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

10. 10 Overcoming Technical Hardships Real Time Algorithms High Speed Synchronization Data Masses Handling Decryption and Descrambling Extensive Spec Survey המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

11. 11 PCI-Express Analyzer המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory A Mother Board Stub Switch B PCI-Express Analyzer Line Sniffing Data Sampling Analyzing and Filtering Displaying Results Header

12. 12 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory PCIe Analyzer –Arch. Gigabit Receiver 1 1 Decryption Module 2 Wrap Filter 3 Packet Filter 4 MSU Control 5 Link Assessment 6 2 34 5 6 Memory Controller 7 Central Controller 8 7 8 Physical Transaction Physical Data Link Transaction Physical Data Link

13. 13 Originality Minimized – Synthesis Oriented Programming Unique Algorithm Development Mathematical – Logical Solutions Optimized Performance Code - 10,000 Lines Open Source Embedded PCIe Generator המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

14. 14 Innovation Minimization - Entire System on Single Chip Unique Tool using Standard Hardware (300$) Minimal Resources yield Maximal Result Real Time Hardware Processing Open Code flexibility Embedded into System under Test המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

15. 15 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory PEAC – TOP Block Diagram

16. 16 Project Development Process High Speed Communication Fundamentals Semester A Final Concept Requirements Doc PCI Express Architecture Concepts market survey Current Available Products Existing Infrastructure Constructing Analyzer Core Building Blocks Semester B Analyzer Core Development report Debugging & Testing Each block Final Core Integration המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

17. 17 הטכניון - מכון טכנולוגי לישראל Technion - Israel institute of technology Kasher Award Finals Performed by : Samuel Amir, Danny Volkind Instructed by : Mr. Orbach Mony Assisted by : Mr. Eli Shosan Traffic Analyzer Core