1. VLVNT Amsterdam 2003 – J. Panman1 DAQ: comparison with an LHC experiment J. Panman CERN VLVNT workshop 7 Oct 2003 Use as example CMS (slides taken from Cittolin's talk at LHCC) Take numbers floating around this week as typical performance needs

2. VLVNT Amsterdam 2003 – J. Panman1 Data to shore: links per tower/string1 data rate/link1.6 Gbits/s total data rate640 Gbits/s Comparison of design parameters Take numbers floating around this week as typical performance needs For simplicity: use a “digitized scenario” (waveforms transmitted) Data source: sampling frequency200-400 Mhz sampling precision8 bits sample length50-100 ns No. OMs10000 No. towers/strings400 Background rate50-200 kHz/OM Event organization: “Event” window length10 ms size of data/event800 Mb

3. VLVNT Amsterdam 2003 – J. Panman1 Data to shore: links per tower/string1 data rate/link1.6 Gbits/s total data rate640 Gbits/s Comparison of design parameters Take numbers floating around this week as typical performance needs For simplicity: use a “digitized scenario” (waveforms transmitted) Data source: sampling frequency200-400 Mhz sampling precision8 bits sample length50-100 ns No. OMs10000 No. towers/strings400 Background rate50-200 kHz/OM Event organization: “Event” window length10 ms size of data/event800 Mb Data to surface: Average event size1 Mbyte No. FED S-link64 ports700 DAQ links (2.5 Gb/s) 512+512 Event fragment size2 kB FED builders (8x8 dual)64 Technology(2004)Myrinet Total data rate: total data rate800 Gbits/s CMS

4. VLVNT Amsterdam 2003 – J. Panman1 Credits slides taken from Cittolin's talk at LHCC

5. VLVNT Amsterdam 2003 – J. Panman1 Front end Desktop/Server current architecture Peripheral IObus PCI: 33/66 MHz x 32/64 bit 100/200/400 MB/s Pxx MEM Pxx 264 MB/s GByte memory MultiProcessor PCI 264 MB/s Dual PCI 1990' PCI Pxx SIO MEM 200X: PCI-X … FE digitizer Data from a string DSP-like operation: filter produces time&charge from waveform assume 8 bytes to encode (reduction x3) Data from a string Readout network

6. VLVNT Amsterdam 2003 – J. Panman1 Network configurations EVB staging by switch expansion: FED -> FE digitizer

7. VLVNT Amsterdam 2003 – J. Panman1 CMS – 2 stages: Data to surface & Readout Builder Readout Builder (up to 8) 64x64 x 2.5 Gb/s switch Event rate 12.5 kHz 2 kByte 16 kByte Data to surface (rate decimation) FED Builder (64 units) 8x8 x 5 Gb/s switch Event fragments merger

8. VLVNT Amsterdam 2003 – J. Panman1 CMS – DAQ staging : 2 RBs = 25 kHz FED Builders Programmed to send events to two output (odd and even EvNo.) Data to surface (rate decimation) Readout Builders (modular staging)

9. VLVNT Amsterdam 2003 – J. Panman1 CMS – DAQ staging : 8 RBs = 100 kHz Data to surface (rate decimation) Readout Builders (modular staging)

10. VLVNT Amsterdam 2003 – J. Panman1 CMS – 3-D DAQ implementations and scaling Readout Builders (x8): Lv-1 max. trigger rate12.5 kHz RU Builder (64x64).125 Tbit/s Event fragment size16 kB RU/BU systems64 Event filter power10 5 SI95 EVB technology (2006)Open Data to surface: Average event size1 Mbyte No. FED S-link64 ports700 DAQ links (2.5 Gb/s) 512+512 Event fragment size2 kB FED builders (8x8 dual)64 Technology(2004)Myrinet

11. VLVNT Amsterdam 2003 – J. Panman1 Comparison of numbers Total data rate of km3 detector similar to an LHC detector after the L1 trigger Number of data sources similar to number of FE Digitizers Waveform filtering (if possible) reduces the data volume by factor 3 Moore's law will help by factor 4-8 compared to LHC Output rate of HLT farm in km3 (presumably) much lower than 100 Hzx1Mb Probably data storage problem much smaller than LHC HLT processing time/byte looks to be smaller than at LHC (LHC has to reject real physics events)

12. VLVNT Amsterdam 2003 – J. Panman1 Summary DAQ architecture of LHC experiments can be a useful starting point for a design Similar techniques, but probably smaller requirements A couple of years later: profit from experience profit from performance/price ratio trend At a first glance the DAQ does look feasable