1. S. Brambilla, “Recent DAQ integration test at L.N.L. 05-09 May 2008” 7 th AGATA Week, Uppsala, 8-11 July 2008 7 th AGATA Week Uppsala, 8-11 July 2008 Recent DAQ integration test at L.N.L. 05-09 May 2008 S. Brambilla I.N.F.N. Sezione di Milano

2. S. Brambilla, “Recent DAQ integration test at L.N.L. 05-09 May 2008” 7 th AGATA Week, Uppsala, 8-11 July 2008 Test Goals: VME test bench from I.N.F.N. Milano has been used check the AGAVA CBLT functionalities at realistic trigger rates probe the compatibility of the AGAVA production release with the new version of the GTS (GTS release 2), based on the Virtex 4 FPGA STRUCK SIS1100/SIS3100 PCI/cPCI to VME interface AGAVA board release 1 and 2, GTS release 1 and 2 CAEN V775 32 channel TDC CAEN V785 32 channel ADC CAEN V538A 8 channel NIM-ECL/ECL-NIM Translator CBLT sequence: Agava, TDC, ADC NIM Repetitive pulser at 20KHz

3. S. Brambilla, “Recent DAQ integration test at L.N.L. 05-09 May 2008” 7 th AGATA Week, Uppsala, 8-11 July 2008 Software environment: Kmax dedicated application was used to control the VME modules. STRUCK board is equipped with DSP, memory and NIM and ECL I/O - Readout has been performed by the DSP (SHARC ADSP-21062L) Events stored and presorted in circular buffers (800 events x buffer) - Buffers readout and online sorting by kmax software DSP Acquisition logic: wait local trigger (Struck Lemo1 input) wait validation (Struck Lemo2 input) wait AGAVA, TDC and ADC data ready (single vme access) CBLT or standard readout of AGAVA, TDC and ADC modules Integrity check of the event (header, data and trailers) Check event counter alignment for TDC and ADC Buffer handling

4. S. Brambilla, “Recent DAQ integration test at L.N.L. 05-09 May 2008” 7 th AGATA Week, Uppsala, 8-11 July 2008

5. S. Brambilla, “Recent DAQ integration test at L.N.L. 05-09 May 2008” 7 th AGATA Week, Uppsala, 8-11 July 2008

6. S. Brambilla, “Recent DAQ integration test at L.N.L. 05-09 May 2008” 7 th AGATA Week, Uppsala, 8-11 July 2008 Test summary: Acquisition rate ≈ 10KHz both in single and in CBLT access System stability: 8 hours test without any problem (repetitive) All the ≈ 300 Ml. of events were good and well formatted VME standard compatibility tests and functionality of the AGAVA_2 module with the GTS_2 has been proved Information concerning event trigger and event validation were passed correctly between the AGAVA_2, GTS_2 and external LEMO connector Consistency of Local Trigger Tag / Validation Tag has been verified (new GTS firmware was giving only validation)

7. S. Brambilla, “Recent DAQ integration test at L.N.L. 05-09 May 2008” 7 th AGATA Week, Uppsala, 8-11 July 2008 Front End based on CAEN modules: V775: 32 channels TDC V879: 32 channels TDC V785: 32 channels ADC V878: 32 channels ADC V792: 32 channels QDC V812: 16 channels CFD V560: 16 channels scaler Readout : VME CPU Optical link PCI to VME interface PCI to VME interface: CAEN V2718 STRUCK SIS1100/SIS3100 L.N.L. LINCO CMS board Hardware:

8. S. Brambilla, “Recent DAQ integration test at L.N.L. 05-09 May 2008” 7 th AGATA Week, Uppsala, 8-11 July 2008 Tests with CAEN V2718 PCI to VME controller have been planned Next tests: Use of a dedicated PCI I/O board - Local trigger, validation-reject trigger.. - data ready, reset, fast clear... Extended tests with high rate random pulser or detectors, both with STRUCK SIS1100/SIS3100 and CAEN V2718 pci-to-VME interface

9. S. Brambilla, “Recent DAQ integration test at L.N.L. 05-09 May 2008” 7 th AGATA Week, Uppsala, 8-11 July 2008 Thank you !

10. S. Brambilla, “Recent DAQ integration test at L.N.L. 05-09 May 2008” 7 th AGATA Week, Uppsala, 8-11 July 2008

11. S. Brambilla, “Recent DAQ integration test at L.N.L. 05-09 May 2008” 7 th AGATA Week, Uppsala, 8-11 July 2008 Test with the Struck SIS1100/SIS3100 PCI to VME interface (optical link) PC SetUp: Pentium 4 PC, 3.00 GHz, 1Mb RAM, SIS1100 pci board XP environment and Kmax software VME SetUp: SIS3100 with DSP (ADSP21061L), 512MB memory, NIM-ECL Interface One 32 channel VME TDC (V879) One 32 channel VME ADC (V878) Local latency 1  s for local trigger and GTS latency 6  s for Trigger_Validation and Trigger_Reject from AGAVA board have been simulated using NIM EG&G GG800 Trigger_Request, Trigger_Validation and Trigger_Reject have been carried to the SIS3100 NIM inputs

12. S. Brambilla, “Recent DAQ integration test at L.N.L. 05-09 May 2008” 7 th AGATA Week, Uppsala, 8-11 July 2008 DSP is controlled by Kmax using common shared memory DSP receives triggers and organise data into memory in 4 buffers of 32000 longwords Local events are composed of 12 longwords (8 data plus headers and trailers) Buffers are read by Kmax as single memory blocks Trigger_Reject has been done by 2 single broadcast DSP VME cycle Test done both in single accesses and in CBLT mode

13. S. Brambilla, “Recent DAQ integration test at L.N.L. 05-09 May 2008” 7 th AGATA Week, Uppsala, 8-11 July 2008