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LHCb-week June 2005 OT 1 Dirk Wiedner 1 MHz Readout and Zero Suppression for the Outer Tracker Dirk Wiedner, Physikalisches Institut der Universität Heidelberg.

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Presentation on theme: "LHCb-week June 2005 OT 1 Dirk Wiedner 1 MHz Readout and Zero Suppression for the Outer Tracker Dirk Wiedner, Physikalisches Institut der Universität Heidelberg."— Presentation transcript:

1 LHCb-week June 2005 OT 1 Dirk Wiedner 1 MHz Readout and Zero Suppression for the Outer Tracker Dirk Wiedner, Physikalisches Institut der Universität Heidelberg

2 LHCb-week June 2005 OT 2 Dirk Wiedner FE-Data Overview 1 optical link/FE-box: 128 channel Data Data = header+drifttime 1-2 O-RxCards/TELL19 9 optical links per O-Rx 9 (18) x 128 channels 6 % expected occupancy 4 x OTIS TDC Data GOL-Aux Board O-RxCard TELL1 FE-Box 9 x 1 (2) x

3 LHCb-week June 2005 OT 3 Dirk Wiedner Zero suppression algorithm outline A)Hit-Pattern Data Format One Hit bit for each OT Straw-Channel Fixed event size: 172 (334) byte per TELL1 B)Zero-suppressed Data Format Channel Address for valid hits Variable event size: 172 (334) bytes @ 11.5% occupancy

4 LHCb-week June 2005 OT 4 Dirk Wiedner Implementation for Hit-Pattern Data Format Extract Bunch-ID, L0-ID, Detector Location from TDC header Generate Bank header, TELL1 header, GOL header Parse the incoming OT data stream for non-zero drift time, set hit-bit Rearrange Data and output to L1 link-wise: 1 Byte GOL-address, 16 bytes Hit-Pattern

5 LHCb-week June 2005 OT 5 Dirk Wiedner... TDC 0TDC 35 HEADER DATA GOL0 TDC 3 TDC2 TDC1 TDC0 GOL8 TDC35 TDC34 TDC33 TDC32... BANK HEADER TELL1 HEADER GOL HEADER HIT-PATTERN DATA Front End L1 Farm Switch

6 LHCb-week June 2005 OT 6 Dirk Wiedner Implementation for Zero-suppressed Data Format Build data headers as for Hit-pattern Parse incoming OT data stream Generate an address byte for each non zero drift time (counter from 0 to 127) Count the number of hits in each link Output data link-wise: GOL address and number of hits (2 bytes) Address of hit channels (1 byte each)

7 LHCb-week June 2005 OT 7 Dirk Wiedner Expected Performance Pipelined architecture: Latency for Data sync. and extraction ~40 cycles Latency for building Header ~10 cycles Data output 86 (167) cycles for Hit Pattern Data 136 (217) cycles delay between first bit in and last output bit Event size full OT: Hit Pattern: 48 (24) TELL1 x 172 (334)= 8256 (8016) [Bytes] Zero supp.: 48 (24) TELL1 x (28 (46) + occ.[%] x ca.14 (28)) Bytes 8256 (8016) Bytes @ 11.5% occ., 5664 (5424) Bytes @ 6 % occ.

8 LHCb-week June 2005 OT 8 Dirk Wiedner Impact on data quality Both schemes (hit-pattern and zero suppression) give up drift times: Space resolution 2.5/ mm instead of 200 μm Zero suppression scheme can be upgraded to combine 2 straw tube layers: Resolution ~300 μm Solved ambiguities 5664 (5424) Bytes/Event @ 6% occupancy

9 LHCb-week June 2005 OT 9 Dirk Wiedner Current status Current algorithm is used for 4-6 link readout Full OT data input synchronization and error checking Reformatting for SDRAM or PCI output Output format: TDC 0 header + full TDC 0 data TDC 1 header + full TDC 1 data...

10 LHCb-week June 2005 OT 10 Dirk Wiedner Summary Output of Hit-pattern or Zero-suppressed Data Format possible @ 1.1 MHz OT Eventsize ≤ 8256 (8016) Bytes Single channel resolution 2.5/ mm Pipelined algorithm ca. 3.4 (5.5) μs full latency Current data formatting can be modified to suggested 1 MHz schemes

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