1. Architectural and Physical Design Optimization for Efficient Intra-Tile Communication Liza Rodriguez Aurelio Morales EEL 6935 - Embedded Systems Dept. of Electrical and Computer Engineering University of Florida By: A. Papanikolaou, F. Starzer, M. Miranda, K. de Bosschere, F. Catthoor

2. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 2 of 32 Outline Introduction Introduction Related Work Related Work Intra-Tile Segmented Buses Intra-Tile Segmented Buses System Architecture Case Study System Architecture Case Study Results Results Conclusions Conclusions

3. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 3 of 32 Outline Introduction Introduction Related Work Related Work Intra-Tile Segmented Buses Intra-Tile Segmented Buses System Architecture Case Study System Architecture Case Study Results Results Conclusions Conclusions

4. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 4 of 32 Inter-Tile Architectures Take care of communication between tiles Significant latency can be tolerated. Intra-Tile Architectures Provide means for transferring data between components of the same tile (Mems, PEs). Communication Bandwidth is large (Gbps). Low latency (1 or 2 cycles). Energy per transfer should be very low. Communication Architectures in SoC Introduction

5. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 5 of 32 Introduction Inter-Tile and Intra-Tile Communication in a SoC

6. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 6 of 32 System On-Chip Communication Architectures Buses are the simplest and most widely used SoC interconnection networks. Bus: a collection of signals (wires) to which one or more IP components are connected. Only one IP component can transfer data on the shared bus at any given time. Micro- controller Digital Signal Processor Input/ Output Device Memory Bus Buses

7. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 7 of 32 Bus Terminology © 2008 Sudeep Pasricha & Nikil Dutt Master (or Initiator) IP component that initiates a read or write data transfer Slave (or Target) IP component that does not initiate transfers and only responds to incoming transfer requests Arbiter Controls access to the shared bus Uses arbitration scheme to select master to grant access to bus Decoder Determines the target for any transfer initiated by a master Bridge Connects two busses Acts as slave on one side and master on the other

8. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 8 of 32 Bus signal lines A bus typically consists of three types of signal lines ◦ Address  Carry address of destination for which transfer is initiated  Can be shared or separate for read, write data ◦ Data  Carry information between source and destination components  Can be shared or separate for read, write data ◦ Control  Requests and acknowledgements  Specify more information about type of data transfer  Byte enable, burst enable address lines data lines control lines

9. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 9 of 32 Types of Bus Topologies Shared bus © 2008 Sudeep Pasricha & Nikil Dutt

10. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 10 of 32 Hierarchical shared bus © 2008 Sudeep Pasricha & Nikil Dutt Improves system throughput Multiple ongoing transfers on different buses Types of Bus Topologies

11. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 11 of 32 Split bus © 2008 Sudeep Pasricha & Nikil Dutt Reduces impact of capacitance across two segments Reduces contention and energy Types of Bus Topologies

12. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 12 of 32 Full crossbar/matrix bus (point to point) © 2008 Sudeep Pasricha & Nikil Dutt Other Topologies

13. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 13 of 32 Bus Physical Structure tri-state buffer based bidirectional signals Commonly used in off-chip/backplane buses ▫ + take up fewer wires, smaller area footprint ▫ - higher power consumption, higher delay, hard to debug © 2008 Sudeep Pasricha & Nikil Dutt

14. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 14 of 32 MUX based signals © 2008 Sudeep Pasricha & Nikil Dutt Separate read, write channels Bus Physical Structure

15. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 15 of 32 Introduction Motivation Communication is one of most critical aspect affecting system performance in current SoC. Communication architecture consumes up to 50% of total on-chip power. Ever increasing number of wires, repeaters, bus components (arbiters, bridges, decoders etc.) increases system cost. Communication architecture design, customization, exploration, verification and implementation takes big part of the design cycle.

16. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 16 of 32 Introduction Proposal Design of a scalable and energy-efficient programmable communication architecture for SoCs. Application domain specific SoC, with a software- controlled implementation of segmented buses for intra- tile communication for energy savings and delay/latency gains.

17. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 17 of 32 Agenda Introduction Introduction Related Work Related Work Intra-Tile Segmented Buses Intra-Tile Segmented Buses System Architecture Case Study System Architecture Case Study Results Results Conclusions Conclusions

18. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 18 of 32 Past and current research have been focused on communication between SoC tiles. Use of standards: AMBA Bus (ARM) [3] CoreConnect (IBM) [4] STBus (ST Microelectronics) [5] WISHBONE (Opencores.org) [6] Academic Contributions: NoC [7][8] Self-Timed segmented buses [9] Previous work on segmented buses focused on architecture optimization, ignoring physical aspects. Related Work

19. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 19 of 32 AMBA (Advanced Microcontroller Bus Architecture)

20. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 20 of 32 PLB (Processor Local Bus) PLB (Processor Local Bus) Pipelined Burst modes Split transactions Multiple masters OPB (On-chip Peripheral Bus) OPB (On-chip Peripheral Bus) Low bandwidth Burst mode Multiple Masters DCR (Device Control Register) DCR (Device Control Register) Low throughput 1 r/w = 2 cycles Ring type data bus IBM CoreConnect

21. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 21 of 32 Agenda Introduction Introduction Related Work Related Work Intra-Tile Segmented Buses Intra-Tile Segmented Buses System Architecture Case Study System Architecture Case Study Results Results Conclusions Conclusions

22. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 22 of 32 Architecture of Segmented Buses Communication Network Communication between PEs and local memories involves large BW. Latency should be minimal to reduce stall cycles. To meet requirements of low energy, low latency, and high BW: Use of software-controlled segmented buses. Buses are divided into segments. Use of tri-state switches. Energy Optimal Segmented Bus (ESB) Architecture

23. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 23 of 32 Data Plane Infrastructure that provides the means for the transfer of data from source to destination. Buses and switches. Issues: number of parallel buses, and where to insert the switches. Assumption: application is fully characterizable at compile-time. Switches can be unicast or multicast Control Plane Infrastructure that provides the correct routing of data. Communication Control block & Control Decoding Logic are part of Control Plane. Communication conflicts are resolved at compile and synthesis time.

24. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 24 of 32 Outline Introduction Introduction Related Work Related Work Intra-Tile Segmented Buses Intra-Tile Segmented Buses System Architecture Case Study System Architecture Case Study Results Results Conclusions Conclusions

25. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 25 of 32 Single-Tile in a SoC. Three hardwired datapaths (demodulator with FFT processor, deinterleaver, Viterbi decoder) and 9 working memories. Communication architecture is clustered into 3 set of segmented buses. Each switch is controlled by the network controller. Digital Audio Broadcast (DAB) Receiver Block diagram of a DAB receiver [11]

26. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 26 of 32 Architectural Optimizations Switches were clustered into groups. Communication Architecture Optimization System Partitioning Partition the system into non-communicating clusters. No memory have access to more than one datapath port. Data and address buses that connect memories to datapaths are partitioned into three smaller buses. Physical Design Optimization Floorplan is generated according to block’s comm. activities. Highly active memories are placed close to its PE.

27. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 27 of 32 Outline Introduction Introduction Related Work Related Work Intra-Tile Segmented Buses Intra-Tile Segmented Buses System Architecture Case Study System Architecture Case Study Results Results Conclusions Conclusions

28. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 28 of 32 Results Area breakdown of DAB using the Segmented Bus Architecture Break down of Storage Energy and Data Transfer for the DAB @ 130nm. Measurement unit is Joules. Critical path in segmented bus communication architecture was 1.8 ns. Critical memory access time was 2.5 ns.

29. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 29 of 32 Outline Introduction Introduction Related Work Related Work Intra-Tile Segmented Buses Intra-Tile Segmented Buses System Architecture Case Study System Architecture Case Study Results Results Conclusions Conclusions

30. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 30 of 32 Communication is becoming a significant part of energy consumption in SoC designs. Use of software-controlled implementation of segmented buses provided the required latency and bandwidth for intra-tile communication. Significant energy savings compared to using single shared bus. Conclusions

31. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 31 of 32 References [1] A. Papanikolaou et al ”Architectural and Physical Design Optimizations for Efficient Intra-tile Communication”, Proceedings of the 2005 International Symposium on System-on-Chip, 17-17 Nov. 2005, pp 112 – 115, http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=01595657 http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=01595657 [2] S. Pasricha, N. Dutt, “On-Chip Communication Architectures: System on Chip Interconnect”, Morgan Kaufmann, 2008. [3] ARM, AMBA Bus specification,available at: http://www.arm.com/products/system-ip/amba/index.php http://www.arm.com/products/system-ip/amba/index.php [4] IBM, CoreConnect Bus Architecture, available at: https://www-01.ibm.com/chips/techlib/techlib.nsf/products/CoreConnect_Bus_Architecture [5] ST Microelectronics, STBus specifications, available at: http://www.st.com/stonline/products/literature/um/14178.pdf [6] WISHBONE specifications http://www.opencores.org/downloads/wbspec_b3.pdf http://www.opencores.org/downloads/wbspec_b3.pdf [7] W. Dally, B. Towles, "Route packets, not wires: on-chip interconnection networks", Design Automation Conf, June 2001, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=935594 http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=935594 [8] L.Benini, G. De Micheli, "Networks on chips: a new SoC paradigm", IEEE Computer, Jan. 2002. [9] J. Plosila, T. Seceleanu, P. Liljeberg, "Implementation of a self-timed segmented bus", IEEE Design & Test of Computers, Nov. 2003, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1246163 http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1246163 [10] J. Guo et al, “Topology exploration for energy efficient intra-tile communication”, Design Automation Conference, 2007, pp 178 – 183, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4196028 http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4196028 [11] K. Taura et al “A digital Audio Broadcasting (DAB) Receiver” IEEE Transactions on Consumer Electronics, 1996, pp 322 – 327, http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=00517204 http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=00517204

32. EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 32 of 32 Questions?