1. South Bridge North Bridge I2CI2C SPI GPIO I2CI2C SPI GPIO FTSH Micro-B SMA JTAG USB Clock RJ45 GPIO RGMII AFE Analog UART

2. ETH PHY South Bridge North Bridge VSUP - 3.6V ~ 5V D3V3 - Digital 3.3VD1V5 - Digital 1.5V A1V5 - Analog 1.5V A3V3 – Analog 3.3V AFE

3. SmartFusion FPGA fabric MSS CCC CCC USB CLKLP XTAL MAIN CLK IN EXT CLK IN REF CLK OUT EXT CLK OUT RMII CLK AFE 1 CLK AFE 2 CLK MSS 32 kHz OSC GLC GLB GLA0 PLL 20 MHz from SMA 20 MHz from TCXO 32 kHz from XTAL 50 MHz from ETH OSC 60 MHz from USB chip max. 20 MHz to AFEs (DDR) 20 MHz (differential) to mezzanine 20 MHz to SMA 100 MHz RC OSC

4. SmartFusion FPGA fabric MSS CCC CCC USB CLKLP XTAL MAIN CLK IN EXT CLK IN REF CLK OUT EXT CLK OUT RMII CLK AFE 1 CLK AFE 2 CLK MSS 32 kHz OSC GLC GLB GLA0 PLL GLC 20 MHz from SMA 20 MHz from TCXO 32 kHz from XTAL 50 MHz from ETH OSC 60 MHz from USB chip max. 20 MHz to AFEs (DDR) 20 MHz (differential) to mezzanine 20 MHz to SMA

5. SmartFusion FPGA fabric MSS CCC CCC USB CLKLP XTAL MAIN CLK IN EXT CLK IN REF CLK OUT EXT CLK OUT RMII CLK AFE 1 CLK AFE 2 CLK MSS 32 kHz OSC GLC GLB GLA0 PLL GLC 20 MHz from SMA 20 MHz from TCXO 32 kHz from XTAL 50 MHz from ETH OSC 60 MHz from USB chip max. 20 MHz to AFEs (DDR) 20 MHz (differential) to mezzanine 20 MHz to SMA

6. SMA AFE 1 AFE 2 Mezzanine SMA XTAL OSC USB chip ETH PHY TCXO EXT CLK IN MAIN CLK IN 20 MHz LP XTAL 32 kHz RMII CLK 50 MHz USB XTAL 12 MHz USB CLK 60 MHz EXT CLK OUT 20 MHz AFE 1 CLK max. 20 MHz AFE 2 CLK REF CLK OUT 20 MHz (differential)

7. ETH PHY South Bridge North Bridge VSUP D3V3D1V5 A1V5A3V3 ADC, DAC

10. SRAM South Bridge North Bridge I2CI2C SPI GPIO I2CI2C SPI GPIO FTSH SMA Jack/BNC Analog JTAG Clock I/O Analog LED GPIO EMI

11. SmartFusion FPGA fabric MSS CCC CCC USB CLK LP XTAL MAIN CLK IN EXT CLK IN REF CLK OUT EXT CLK OUT RMII CLK AFE1 CLK AFE2 CLK MSS ETH PHY 32 kHz OSC GLC GLB GLA0 PLL CLKC

12. SmartFusion Fabric CCC MSS CCC CCC USB CLK LP XTAL MAIN CLK IN EXT CLK IN REF CLK OUT EXT CLK OUT RMII CLK AFE1 CLK AFE2 CLK MSS ETH PHY 32 kHz OSC GLC GLB GLA0 PLL CLKC

13. SmartFusion FPGA Fabric CCC MSS CCC CCC USB CLK LP XTAL MAIN CLK IN EXT CLK IN REF CLK OUT EXT CLK OUT RMII CLK AFE1 CLK AFE2 CLK MSS ETH PHY 32 kHz OSC DUT GLC GLB GLA0 PLL CLKC

14. FPGA Fabric CCC MSS CCC CCC USB CLK LP XTAL MAIN CLK IN EXT CLK IN REF CLK OUT EXT CLK OUT RMII CLK AFE1 CLK AFE2 CLK MSSETH PHY 32 kHz OSC DUT GLC GLB GLA0 PLL

15. FPGA Fabric CCC MSS CCC CCC USB CLK LP XTAL MAIN CLK IN EXT CLK IN REF CLK OUT EXT CLK OUT RMII CLK AFE1 CLK AFE2 CLK MSSETH PHY 32 kHz OSC DUT GLC GLB GLA0 PLL

16. CCC MSS CCC CCC USB CLK LP XTAL MAIN CLK IN EXT CLK IN REF CLK OUT EXT CLK OUT ETH CLK AFE1 CLK AFE2 CLK MSS ETH PHY

17. CCC USB CLKLP XTAL MAIN CLK IN EXT CLK IN REF CLK OUT EXT CLK OUT ETH CLK