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Anshul Kumar, CSE IITD CSL718 : Superscalar Processors Issue and Despatch 23rd Jan, 2006.

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Presentation on theme: "Anshul Kumar, CSE IITD CSL718 : Superscalar Processors Issue and Despatch 23rd Jan, 2006."— Presentation transcript:

1 Anshul Kumar, CSE IITD CSL718 : Superscalar Processors Issue and Despatch 23rd Jan, 2006

2 Anshul Kumar, CSE IITD slide 2 Early proposals/prototypes 1982 1983 1984 1985 1986 1987 1988 1989 IBM DEC Stanford U Kyushu U CheetahAmerica project(4) Multititan project(2) Match(2) Torch(4) SIMP(4) DSNS(4) Term Superscalar

3 Anshul Kumar, CSE IITD slide 3 Commercial superscalars RISCs Intel960KA/KB  960CA (3)1989 IBMPower 1 RS/6000 (4)1990 HPPA7000  PA7100 (2)1992 SUNSPARC  SuperSparc (3)1992 DECAlpha 21064(2)1992 MotorolaMC88100  MC88110(2)1993 MotorolaPowerPC 601/603 (3)1993 MIPSR4000  R8000(4)1994

4 Anshul Kumar, CSE IITD slide 4 Commercial superscalars CISCs Intel80486  Pentium (2)1993 Motorola MC68040  MC68060 (2)1993 GmicroGmicro/100p  Gmicro 500 (2)1993 AMDK5(2) – 4 RISC instr 1995 CYRIXM1 (2)1995

5 Anshul Kumar, CSE IITD slide 5 Tasks of superscalar processing Parallel Parallel Preserving the decoding instruction sequential and issue execution consistency of instruction execution and exception processing

6 Anshul Kumar, CSE IITD slide 6 Superscalar decode and issue I - cache Instruction buffer Decode & Issue IFD/I I - cache Instruction buffer Decode & Issue IFDI Scalar Issue Superscalar Issue

7 Anshul Kumar, CSE IITD slide 7 Parallel Decoding Fetch multiple instructions in instruction buffer Decode multiple instructions in parallel – instruction window Possibly check dependencies among these as well as with the instructions already under execution

8 Anshul Kumar, CSE IITD slide 8 Pre-decodingPre-decoding Do partial decoding while instructions are being loaded in I-cache Decoded information is appended to the instruction This includes instruction class, resources required etc. Second level cache or main memory Pre-decode unit I - cache N bits/cycle N + n bits/cycle

9 Anshul Kumar, CSE IITD slide 9 Number of Pre-decode bits ProcessorNo. of predecode bits PA 7200 (1995)5 PA 8000 (1996)5 PowerPC 620(1996)7 UltraSparc (1995)4 HAL PM1 (1995)4 AMD K5 (1995)5 (per byte) R 10000 (1996)4

10 Anshul Kumar, CSE IITD slide 10 Issue vs Dispatch Blocking Issue Decode and issue to EU Instructions may be blocked due to data dependency Non-blocking Issue Decode and issue to buffer From buffer dispatch to EU Instructions are not blocked due to data dependency

11 Anshul Kumar, CSE IITD slide 11 Blocking Issue EU Decode Check & Issue Instruction buffer issue window

12 Anshul Kumar, CSE IITD slide 12 Non-blocking (shelved) Issue Reservation station Dep. Checking/ dispatch EU Reservation station Dep. Checking/ dispatch EU Reservation station Dep. Checking/ dispatch EU Decode & Issue Instruction buffer

13 Anshul Kumar, CSE IITD slide 13 Handling of Issue Blockages Preserving issue order Alignment of instruction issue aligned unaligned in-order out of order

14 Anshul Kumar, CSE IITD slide 14 Issue Order cdabe a Issue window Instructions to be issued Instructions issued cdabe a Issue window Instructions to be issued Instructions issued Issue in strict program orderOut of order Issue c Example: MC 88110, PowerPC 601 Independent instruction Dependent instruction Issued instruction

15 Anshul Kumar, CSE IITD slide 15 AlignmentAlignment cdabe a fixed window checked in cycle 1 Aligned IssueUnaligned Issue issued in cycle 1 fgh next window cdbe b checked in cycle 2 issued in cycle 2 fgh de d checked in cycle 3 issued in cycle 3 fgh c cdabe a gliding window fgh cdbe b fgh defgh c def

16 Anshul Kumar, CSE IITD slide 16 Design choices in instruction issue Coping with Coping with Use of Handling of Issue false data unresolved shelving issue blockages rate dependencies control (2-6) dependencies no Register renaming wait speculative blocking shelved

17 Anshul Kumar, CSE IITD slide 17 Frequently used issue policies in scalar processors Traditional Traditional scalar issue scalar issue with shelving with shelving with spec. and renaming execution CDC 6600IBM 360/91i386 MC68030 R3000 Sparc I486 MC68040 R4000 MicroSparc

18 Anshul Kumar, CSE IITD slide 18 Frequently used issue policies in super scalar processors Straightforward Straightforward Straight forward Advanced superscalar superscalar issue issue with issue with issue shelving renaming (renaming+shelving) aligned unaligned (speculative execution in all) Pentium PowerPC601 PA7100 SuperSparc Alpha21164 MC68060 PA7200 UltraSparc MC88110 R8000 PowerPC602 R10000 PentiumPro PowerPC602 PA8000 Sparc64 Am29000 K5

19 Anshul Kumar, CSE IITD slide 19 Frequently used issue policies Traditional Traditional Straight forward Advanced scalar issue scalar issue superscalar issue superscalar with spec. Issue execution aligned unaligned

20 Anshul Kumar, CSE IITD slide 20 Design Space of Shelving Scope of Layout of Operand fetch Instruction shelving shelving policy dispatch scheme buffers partial full

21 Anshul Kumar, CSE IITD slide 21 Layout of Shelving Buffers Type of the Number of Number of read shelving buffers shelving buffer entries and write ports Stand combined with alone renaming and (RS) reordering individual 2-4 group 6-16 central 20 total 15-40 depends on no. of EUs connected

22 Anshul Kumar, CSE IITD slide 22 Reservation Stations (RS) EU RS Individual RSsGroup RSsCentral RS

23 Anshul Kumar, CSE IITD slide 23 Combined Buffer (for Shelving, Renaming, Reordering) EU DRIS From decode/issue Deferred scheduling, Register renaming and Instruction Shelving

24 Anshul Kumar, CSE IITD slide 24 Operand Fetch Policies Issue bound fetch Dispatch bound fetch

25 Anshul Kumar, CSE IITD slide 25 Issue bound operand fetch (with single register file) EU RS EU RS Decode/issue RF instruction data

26 Anshul Kumar, CSE IITD slide 26 Dispatch bound operand fetch (with single register file) EU RS EU RS Decode/issue instruction data RF

27 Anshul Kumar, CSE IITD slide 27 Issue bound operand fetch (with multiple register files) EU RS EU RS Decode/issue RF instruction data

28 Anshul Kumar, CSE IITD slide 28 Dispatch bound operand fetch (with multiple register files) EU RS EU RS Decode/issue instruction data RF

29 Anshul Kumar, CSE IITD slide 29 Updating RFs and RSs EU RS EU RS Decode/issue RF instruction data

30 Anshul Kumar, CSE IITD slide 30 Instruction dispatch scheme Dispatch Dispatch Checking Treatment of policy rate operand empty RS availability single multiple instr/ cycle Individual RSGroup or central RS

31 Anshul Kumar, CSE IITD slide 31 Dispatch policy Selection Arbitration Dispatch rule rule order Rule for identifying instructions which are ready for execution (data dependency check) Rule for choosing one out of several ready instructions (earlier instruction has priority)

32 Anshul Kumar, CSE IITD slide 32 Dispatch order in-order partially out of out of order order RS check

33 Anshul Kumar, CSE IITD slide 33 Checking availability of operands Direct check of Check of explicit score-board bits status bits in RS (usual for dispatch (usual for issue bound operand fetch) control flow approach data flow approach Flynn’s terminology

34 Anshul Kumar, CSE IITD slide 34 Score-boardScore-board Register File 1 0 1 1 0 0 1 2 Data status Introduced with CDC6600

35 Anshul Kumar, CSE IITD slide 35 Checking in dispatch bound fetch Register File Reservation station OC Rs1 Rs2 Rd EU decoded instruction check V bits of sources update Rd set V bit Rs1,Rs2,Rd reset V bit of Rd OC (opcode) Os1 Os2 (operand value) result, Rd

36 Anshul Kumar, CSE IITD slide 36 Checking in issue bound fetch OC Os1/Is1 Vs1 Os2/Is2 Vs2 Rd EU decoded instruction OC, Os1, Os2, Rd result, Rd Register File update Rd, set V bit Rs1,Rs2,Rd reset V bit of Rd Os1 Os2 (operand value) Reservation station check Vs1, Vs2 associative update of Is1, Is2 with Rd, set Vs bits

37 Anshul Kumar, CSE IITD slide 37 Treatment of an empty RS Straight forward Bypassing approach RS if empty RS At least one cycle stay in RS EU RS EU Nx586 Sparc64 PowerPc 604

38 Anshul Kumar, CSE IITD slide 38 Approaches in dispatching Straight forward Enhanced Advanced in order partially out of order out of order single single multiple instr/cycle instr/cycle instr/cycle individual RSs individual RSs group/central RSs Power1, PPC603 Power2 PM1, PentiumPro Nx586, Am29000 PPC604,620 PA8000, R10000

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