1. June 29th 2005Ph. BUSSON LLR Ecole polytechnique, Palaiseau1 Plans for a new TCC for the endcaps Characteristics: reminder Preliminary list of tasks and milestones

2. June 29th 2005Ph. BUSSON LLR Ecole polytechnique, Palaiseau2 Characteristics: reminder (1) 2 TCCs per 20 degree sector 4 TCCs are connected to 1 Clock and Control System (CCS) board and 1 Data Crate Concentrator (DCC) (2 sectors coverage) VME 64XP, 9U, 20.2 mm width Functions: –Completes Trigger Primitives (TP) computations (ET: total tranvserse energy per trigger tower, FGVB: fine grain veto bit) –Encodes ET using a non linear scale (10 bits ---> 8 bits) –Computes Trigger Tower Flags (TTF, 3 bits) for Selective Readout Processor (SRP) –Stores TP, TTF during L1 accept latency

3. June 29th 2005Ph. BUSSON LLR Ecole polytechnique, Palaiseau3 Characteristics: reminder (2) Receives 4 x 12 optical signals @ 800 Mbits/s (10 bits ET + 1 bit FGVB per pseudo-strip) Sends 16(outer part) or 32(inner part) Trigger Primitives to the Regional Calorimeter Trigger via 2 or 4 Synchro and Link Boards (SLBs) @ 40 MHz, signals are grouped by 8 Sends 16 or 32 Trigger Towers Flags (TTF) to the Selective Readout Processor via 1 serial optical link @ 1600 Mbits/s, L1 accept rate, data format independant of inner/outer: 22 16-bit words Sends 16 or 32 (TP + TTF) to the Data Concentrator Card via LVDS @ 720 Mbits/s, L1 accept rate, data format independant of inner/outer: 37 16-bit words

4. June 29th 2005Ph. BUSSON LLR Ecole polytechnique, Palaiseau4 How to build trigger towers in EE (old geometry, new style mapping) Trigger meeting 11/06/2002

5. June 29th 2005Ph. BUSSON LLR Ecole polytechnique, Palaiseau5 Inputs for TCC Endcap: rule One trunk cable per 20-degree sector ie 8 ribbons of 12 fibers 4 ribbons per TCCEndcap (1 to 4) Order is exclusively driven by outputs, ie 2 signals of TT of type A are sent to the RT (via SLBs) on a single electrical differential pair, 2 signals of TT type B … for each 20-degree sector Trigger Towers we define eta-phi indexes: ieta (1 to 11, from outer towards inner), jphi (1 to 4) Ideal inputs order: ribbon 1 with [pseudo-strips for TT ieta = 1, jphi = 1 to 4]; [ieta = 2, jphi = 1 to 4]; etc … ie we follow the «color lines» (blue&red or yellow&green). The pseudo-strips inputs of one TT can be arranged in any order The PCB of the TCCendcap will be unique ---> exchange of signals between « processors » (the number of processors is not yet known 2,3 or 4) Remark: ribbon order (from top to bottom, or from bottom to top in the front panel) has to be defined within OD team

6. June 29th 2005Ph. BUSSON LLR Ecole polytechnique, Palaiseau6 Task 0 Milestone: setup the TCC48 team by end 09/2005, list of tasks –mechanics, –schematic, –layout, –firmware development, –tests prototype, –reception tests, –software for test bench (XDAQ, HAL) –software online: hardware configuration, monitoring & data quality check (XDAQ, HAL) –software offline: data quality check in reconstruction prog (ORCA) –data base: ConstructionDB, ConfigurationDB, ConditionDB –integration in Off Detector crate at CERN (XDAQ, HAL)

7. June 29th 2005Ph. BUSSON LLR Ecole polytechnique, Palaiseau7 Task 1: prototype From 03/10/2005 to 30/06/2006 –Milestone: finalize list of signals shared between FPGAs 03/11/2005 (ECAL week), 3 cases: 2,3 or 4 FPGAs –Milestone: check that Virtex 4 FX (from Xilinx) - GOH connection is OK (latency budget) 30/10/2005 –Milestone: check that all inputs/outputs, SLBs fit in 20.2 mm width is OK 30/10/2005 –Milestone: board ready for tests 30/04/2006 ---> –Milestone: board ready for production 28/02/2006 –Milestone: completion of modifications for final version 30/06/2006

8. June 29th 2005Ph. BUSSON LLR Ecole polytechnique, Palaiseau8 Task 2 : preproduction, production and reception of final version From 05/06/2006 to 29/09/2007 –Milestone: start production 31/03/2007 –Milestone: start reception 30/05/2007 –Milestone: start integration of first board in Off Detector Crate 29/06/2007 –Milestone: end integration 29/09/2007