1. 1 Building Larger Circuits Today: Combinational Building BlocksFirst Hour: Combinational Building Blocks –Section 4.1 of Katz’s Textbook –In-class Activity #1 Second Hour: Tri-state and Open Collector Gates, ROMs. Section 4.2 of Katz’s Textbook –In-class Activity #2

2. 2 Recap: To simplify large Boolean functions, we use logic minimization software (espresso) We can use multi-level minimization when speed is not a problem. Use Programmable Logic Arrays to implement large circuits in an automated manner. Today: We’ll learn about another tool for building large circuits: higher-level building blocks (modules).

3. 3 Building Blocks MUX DEMUX A B Sum A0A1B0 B1 SaSb Ss S0S1 The Idea: Assemble your system using generic “building blocks.” Examples: PLA Adder, Multiplexor, De-multiplexor, Decoder, Encoder

4. 4 A 2:1 Multiplexor TerminologyTerminology –I 0 and I 1 are input lines –Z is the output line –A is the control signal 2:1 MUX I 0 I 1 A Z AZ0I01I1AZ0I01I1 Truth TableTruth Table Boolean Function: Z = A' I 0 + A I 1 Boolean Function: Z = A' I 0 + A I 1

5. 5 Expanded Truth Table AZ0I01I1AZ0I01I1 I1I0AZ00000010010101101000101111011111I1I0AZ00000010010101101000101111011111

6. 6 Larger MUXes 2:1 MUX I 0 I 1 A Z I 0 A I 1 I 2 I 3 B Z 4:1 MUX I 0 A I 1 I 2 I 3 B Z 8:1 MUX C I 4 I 5 I 6 I 7

7. 7 Cascading MUXes 4:1 MUX 4:1 MUX 8:1 MUX 2:1 MUX 0 1 2 3 0 1 2 3 S S 1 S 0 S 1 S 0 Z A CB I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 0 1

8. 8 Implementing Logic with MUX 2 n-1 :1 n2 n-1 :1 multiplexor can implement any Boolean function of n variables n-1needs n-1 control variables; the remaining variable is used as a data input to the multiplexor Example: F(A,B,C) = m 0 + m 2 + m 6 + m 7 = A' B' C' + A' B C' + A B C' + A B C = A' B' (C') + A' B (C') + A B' (0) + A B (1)

9. 9 Example A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 1 0 1 0 0 0 1 1 C C 0 1 S1 S0 AB 4:1 MUX 0 1 2 3 C C 0 1 F 8:1 MUX 1 0 1 0 0 0 1 1 0 1 2 3 4 5 6 7S2 S1 S0 ABC F

10. 10 De-multiplexors (DMUX) Decoder:n2 nDecoder: single data input, n control inputs, 2 n outputs Sbinary indexcontrol inputs (called selects S) represent binary index of output to which the input is connected Gdata input usually called "enable" (G) Usually Enable = G = 1 Opposite of MUX, also called Decoders

11. 11 2:4 DMUX Select0 Select1 Output2 Output3 Output0 Enable Output1

12. 12 DMUX as a Logic Block 3:8 DMUX (decoder) 0 1 2 3 4 5 6 7 ABC Enable A B C S 2 S 1 S 0

13. 13 Example F1 = A B C D + A B C D + A B C D F2 = A B C D + A B C F3 = (A + B + C + D) Implement the following 4-input, 3-output Boolean function using a decoder (DMUX):

14. 14 A B C D A A A A A A A A A A A A A A A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A S 3 S 2 S 1 S 0 4:16 decoder Enb = 1 BCD F 1 F 3 F 2

15. 15 Do Activity #1 Now Get to know MUX and DMUX building blocks

16. 16 New Kinds of Gates, Read-only Memory New Kinds of Gates, “wired logic”: –3-state output gates –Open-collector gates –Build a MUX easily with these new gates. Read-only Memory (ROM)

17. 17 3-State Gates Three possible outputs: 0, 1, or Z Z means output disconnected Z does not reduce to 1 or 0 OE AB Equivalent Circuit OE A B BZZ10BZZ10Z AXX01AXX01XOE011 Truth Table “output enable”

18. 18 What’s the Big Idea? Allows the output of more than one gate to be connected to the same wire - “wired logic” buses Especially useful for allowing building blocks to exchange data over shared wires - buses Works only as long as only one gate has its output enabled at the same time Device 1 Device 2 Device 3 Bus

19. 19 Multiplexer using 3-State Logic When InputSelect = 1, Input 1 is connected to F When InputSelect = 0, Input 0 is connected to F This is a 2:1 Mux Non-inverting Buffers 3-state Buffer OE Input 0 InputSelect F Input 1

20. 20 Open Collector Gates The output of an open collector gate is like a switch connected to ground output for logic “1”output for logic “0” output for logic “1” output for logic “0” I.C. I.C. Note: If you put a logic probe on an unconnected open- collector pin, it will indicate a logic 0 or nothing. Another way to connect multiple gates to the same output wire

21. 21 Pull-up Resistors I.C. +5V Resistors: 1 - 10 k  typical I.C. +5V Y = 0 Y = 1

22. 22 Two Gates and a Resistor Y becomes 0 when any one switch is closed +5V Y

23. 23 Wired Logic If A and B are 1, Output is actively pulled low If C and D are 1, Output is actively pulled low If one gate is low and the other high, then low wins If both gates are 1, the Output floats. Pull it high with a resistor If A and B are 1, Output is actively pulled low If C and D are 1, Output is actively pulled low If one gate is low and the other high, then low wins If both gates are 1, the Output floats. Pull it high with a resistor Special symbol on OC gates: output bar Output A B C D +5V

24. 24 Output = (A B + C D)' = (A B)' (C D)' = (A' + B')(C' +D') = A' C' + A' D' + B' C' +B' D' So What’s the Big Idea?? Wired Logic !! What is Output(A,B,C,D)? Click for answer  Wired Logic !! What is Output(A,B,C,D)? Click for answer  If A and B are 1, Output is actively pulled low If C and D are 1, Output is actively pulled low If one gate is low and the other high, then low wins If both gates are 1, the Output is pulled up to logic 1. If A and B are 1, Output is actively pulled low If C and D are 1, Output is actively pulled low If one gate is low and the other high, then low wins If both gates are 1, the Output is pulled up to logic 1. Output A B C D +5V

25. 25 Another Practical Issue Useful for lighting Light Emitting Diodes (LEDs) X +5V R I.C. What happens to the LED when X = 1? When X = 0? Click for the answer What happens to the LED when X = 1? When X = 0? Click for the answer No current = OFF Current = ON No current = OFF Current = ON

26. 26 Read-Only Memories Memory Array 2 n words by m bits m output lines n address lines Decoder 2 n word lines Sort of like a PLA structure with a fully decoded AND array! Sort of like a PLA structure with a fully decoded AND array!

27. 27 Applications of ROMs non-volatile Store data in a non-volatile manner Like PLA’s, you can buy programmable ROMs (PROMs) Implement combinational functions

28. 28 ROM vs. PLA ROM advantageous when design time is short (no need to minimize output functions) most input combinations are needed (e.g., code converters) little sharing of product terms among output functionsDownside: size doubles for each additional input can't use don't cares PLA advantageous when design tool like espresso is available there are relatively few unique minterm combinations many shared minterms among the output functions Downside: Downside: constrained fan-ins on OR arrays combinational functions

29. 29 Questions: How many words? How many bits in each word? How many bits overall? Click for answerQuestions: How many words? How many bits in each word? How many bits overall? Click for answer ROM Example 2764 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 O0 O1 O2 O3 O4 O5 O6 O7 OE CS PGM A10 A11 A12 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 O0 O1 O2 O3 O4 O5 O6 O7 OE CS PGM VPP A10 A11 A12 DATALINES(tri-state) ADDRESS LINES OUTPUT ENABLE CHIP SELECT 2 13 = 8K = 8 192 8 2 16 = 64K = 65 536

30. 30 Choices, choices... You can implement logic functions many ways: Existence of alternatives  no clear winner Discrete gates AND/OR NAND/NAND PLAs or PALs Muxes Demuxes (decoders) ROMs

31. 31 Do Activity #2 Now Due: End of Class Today RETAIN THE LAST PAGE (#3)!! For Next Class: Bring Randy Katz Textbook, & TTL Data Book Required Reading: – Sec 5.1 of Katz This reading is necessary for getting points in the Studio Activity!