1. Sept. 2005EE37E Adv. Digital Electronics Lesson 1 CPLDs and FPGAs: Technology and Design Features

2. Sept. 2005EE37E Adv. Digital Electronics Topics Fundamental Concepts CPLDs vs FPGAs CPLD Architectures FPGA Architectures Design Methods for FPGA-based Systems Intellectual Property System-on-chip Reconfigurable Computing Future FPGA Developments

3. Sept. 2005EE37E Adv. Digital Electronics 1. Fundamental Concepts What are CPLDs and FPGAs? –Complex Programmable Logic Devices (CPLDs) and Field Gate Arrays (FPGAs) are digital integrated circuits (ICs) that contain configurable (programmable) blocks of logic along with configurable interconnects between these blocks. –Design engineers can configure (program) such devices to perform a tremendous variety of tasks

4. Sept. 2005EE37E Adv. Digital Electronics Classification of Digital ICs

5. Sept. 2005EE37E Adv. Digital Electronics They thing about CPLDs and FPGAs: The thing that really distinguish an FPGA or a CPLD from an ASIC is the programmable feature. Let us consider a simple programmable function: In order to make our function more interesting, we need some mechanism that allows us to establish one or more of the potential links.

6. Sept. 2005EE37E Adv. Digital Electronics Fusible link technology These fuses are similar in to household fuses.

7. Sept. 2005EE37E Adv. Digital Electronics Programmed fusible links Devices based on fusible-link technologies are said to be one-time programmable, or OTP. FPGAs don’t use them.

8. Sept. 2005EE37E Adv. Digital Electronics Antifuse Technologies Antifuse links are an alternative to fuse links. An antifuse link is programmable by applying a voltage across it. An antifuse is given as follows:

9. Sept. 2005EE37E Adv. Digital Electronics Other Technologies EPROM EEPROM FLASH SRAM

10. Sept. 2005EE37E Adv. Digital Electronics 2. CPLDs vs. FPGAs CPLD architecture Small number of PLDs on a single chip Programmable interconnect between PLDs PLDs = PALs, PLAs,or GALs

11. Sept. 2005EE37E Adv. Digital Electronics FPGA architecture Much larger number of smaller programmable logic blocks. Embedded in a sea of lots and lots of programmable interconnect.

12. Sept. 2005EE37E Adv. Digital Electronics 3. CPLD Architectures Identical individual PLD blocks (Xilinx “FBs”) replicated in different family members. –Different number of PLD blocks –Different number of I/O pins Many CPLDs have fewer I/O pins than macrocells –“Buried” Macrocells -- provide needed logic terms internally but these outputs are not connected externally. –IC package size dictates # of I/O pins but not the total # of macrocells. –Typical CPLD families have devices with differing resources in the same IC package.

13. Sept. 2005EE37E Adv. Digital Electronics Xilinx CPLDs Notice overlap in resource availability in a particular package.

14. Sept. 2005EE37E Adv. Digital Electronics Xilinx 9500-family CPLD architecture 72 ==> XC9572

15. Sept. 2005EE37E Adv. Digital Electronics 9500-family function blocks (FBs) 18 macrocells per FB 36 inputs per FB (partitioning challenge, but also reason for relatively compact size of FBs) Macrocell outputs can go to I/O cells or back into switch matrix to be routed to this or other FBs.

16. Sept. 2005EE37E Adv. Digital Electronics 9500-series macrocell (18 per FB) Up to 5 product terms Programmable inversion or XOR product term Global clock or product-term clock Set control Reset control OE control

17. Sept. 2005EE37E Adv. Digital Electronics 9500-series product-term allocator Share terms from above and below programmable steering elements

18. Sept. 2005EE37E Adv. Digital Electronics 9500-series I/O block

19. Sept. 2005EE37E Adv. Digital Electronics Could be anything from a limited set of multiplexers to a full crossbar. Multiplexer -- small, fast, but difficult fitting Crossbar -- easy fitting but large and slow Switch matrix for XC95108

20. Sept. 2005EE37E Adv. Digital Electronics XC9500 Product Family 9536 Macrocells Usable Gates t PD (ns) Registers Max I/O 3672108144216 8001600240032004800 57.5 10 3672108144216 3472108133166 Packages VQ44 PC44 PC84 TQ100 PQ100 PC84 TQ100 PQ100 PQ160 PQ100 PQ160 288 6400 10 288 192 HQ208 BG352 PQ160 HQ208 BG352 957295108951449521695288

21. Sept. 2005EE37E Adv. Digital Electronics CoolRunner-II CoolRunner-II Family –Lowest system cost using advanced features –Lowest power –High speed –Additional security –Smallest packages Including world ’ s smallest low cost package - QF32 – 1.5V, 1.8V, 2.5V & 3.3V interface – 2 to 4 I/O banks

22. Sept. 2005EE37E Adv. Digital Electronics CoolRunner-II CPLD Architecture AIM: Advanced Interconnect Matrix

23. Sept. 2005EE37E Adv. Digital Electronics