1. A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation Keng-Jan Hsiao and Tai-Cheng Lee National Taiwan University Taipei, Taiwan

2. Outline Motivation System Architecture System Model Circuit Details Experimental Results Conclusion 2

3. Introductions Multiple-Phase Clock Generators –Time-Interleaved System –I/O Interface Circuits –DLL-Based Frequency Multiplier Issues –Phase Accuracy –Jitter Performance 3

4. Conventional DLL Only one output phase is monitored. 4 H.-H. Chang et al, IEEE J. of Solid-State Circuits, May, 2006.

5. DLL with Phase Calibration Circuit Delay cell tuning. Output buffer tuning. 5 Federico Baronti et all, IEEE J. of Solid-State Circuits, Feb., 2004. H.-H. Chang et al, IEEE J. of Solid-State Circuits, May, 2006.

6. Jitter Accumulation Jitter accumulates along the delay line. More delay cells = Larger jitter. 6

7. Distributed DLL(DDLL) All output phases are monitored. Reduce phase mismatch and jitter. 7

8. Locking Process of the DDLL 8 Conceptual demonstration of the DDLL.

9. System Architecture Each delay cell is independently tuned. 9

10. Closed-loop Characteristics 10 Lumped model:

11. Phase Relationship of Multiple-Phases 11 Different clock tracks different Ref. edge.

12. System Model Open-loop Gain: System Function: 12

13. Settling Behavior The simulation result matches the proposed model. 13

14. Stability Constraint The open-loop gain must reduce as the number of delay cells increases. 14

15. Sources of Jitter V n,cell : Noise from delay cells. V n,con : Noise from the control voltage. 15

16. NTF of the Noise of Delay Cells Noise at the last output clock, V p4. 16

17. NTF of the Common Noise Noise at all output phases, V p1 ~V p4. 17

18. Pseudo-differential Delay Cell Pseudo-differential architecture. Differentially controlled. Output buffer isolates output loading. 18

19. Phase Detecter 19 Time Domain Voltage Domain

20. Voltage-to-Current Convertor Continuous-time common-mode feedback. Loop capacitors are realized on-chip. 20

21. Die Photo Active Area = 0.03 mm 2 21

22. Phase Mismatch @ 8GHz 22

23. Phase Mismatch @ 9.5GHz 23

24. 8.5GHz Output Waveform Conventional DLLDistributed DLL RMS Jitter : 643.5fs RMS Jitter : 417.6fs P-P Jitter : 5.67ps P-P Jitter : 4.22ps Contributed Jitter : 578.9fs Contributed Jitter : 308.1fs RMS Jitter of Ref. Clk : 281.0fs 24

25. 10GHz Output Waveform Conventional DLLDistributed DLL RMS Jitter : 443.8fs RMS Jitter : 293.3fs P-P Jitter : 3.18ps P-P Jitter : 2.04ps Contributed Jitter : 366.7fs Contributed Jitter : 153.4fs RMS Jitter of Ref. Clk : 256.8fs 25

26. Performance Comparison 26

27. Conclusion The distributed DLL achieves low jitter and high phase accuracy. Linear model of the proposed distributed DLL is provided. 27

28. Acknowledgement We would like to thank MediaTek Inc. for the support of this project. We would like to thank TSMC for chip fabrication. 28

29. Backup Slides

30. Testing Setup 30