1. Performed By: Yahel Ben-Avraham and Yaron Rimmer Instructor: Mony Orbach Bi-semesterial, 2012 - 2013 18/3/2013

2. Reminder - Project goals  Goal: Extending and analyzing RISC Processor using Bluespec  Part A: Studying the working environment, BSV language and the basic processor implementation. Logical design of processor modifications Theoretical analysis of performance

3. Work flow & progress  Learning Bluespec  Setting up the environment*  Study the simple RISC processor implementation  Assessing modification options.  Logical design of modifications.  Performance analysis and assessing of functional changes (theoretically).  Implementing and testing*.

4. Modifications  Extend the basic RISC processor: 1 st phase: Extend the pipe. 2 nd phase: Add functional capabilities.

5. The working environment  Will use platform by Shai and Dani. Allowing us to focus on the processor.  The platform enables: Synthesis of design to FPGA via Direct PC. Cycle level control using COP. Reading and writing to memories via JTAG.

6. Pipe expansion  Goal: 5-stage pipeline Pipe stages: Fetch, Decode, Execute, Memory, WriteBack Including Data forwarding, Hazard detection.

7. Other capability expansions  Branch prediction 1-bit / 2-bit saturated counter History bits BTB  Cache Replacement policies (LRU…) Read/write policies Indexing

8. Performance analysis  Assess the processor’s capabilities Instructions per cycle Throughput Latency Miss rates More

9. Timeline Assessing modification options.Logical design of modifications. Performance analysis and assessing of functional changes (theoretically). Implementing and testing*Part A final presentation (mid summer)

10. Gantt

11. General Timeline - project Apr Studying modification options and decide on preferable option. Tests, Miluim May Pipe expansion design + theoretical performance analysis Jun Second expansion design + theoretical performance analysis Jul Tests Aug Conclusion, Final presentation

13. Or else…