1. Homework Statement Mao-Cheng Chiu National Chiao -Tung University Department of Electronics Engineering

2. Specification of the TIA Format of report Topology examples Using HSPICE to Analyze Performance Outline

3. Technology 0.18  m CMOS C PD 0.5pF Supply Voltage1.8V Data Rate1.25Gb/s Transimpedance Gain > 10k  -3dB Bandwidth> 1GHz Input Referred Noise Current < 0.15  A rms (1M to 1GHz) OverloadAs large as possible Deterministic Jitter< 100ps pp Power Consumption< 100mW Homework 1: TIA Due Date: May 10, 2007

4. Design Homework –Circuit Architecture –Circuit Analysis –Simulation DC/AC/Noise/Eye diagrams (for sensitivity and overload levels) –Summary Comparison with target spec. Pros & Cons Report Outline

5. Examples of Multi-Stage TIA RFRF M. Ingels, et al., IEEE JSSC, Dec. 1994 S. Yamashita, et al., IEEE JSSC, July. 2002

6. Example: AC analysis Is 0 1 ac 1.ac dec 10 1k 5g.meas ac midgain FIND vdb(vo) AT=100MegHz.meas ac bandwidth when vdb(vo)='midgain-3.0' FALL=1.meas ac maxgain max vdb(vo) Input signal AC analysis Gain & bandwidth.probe Gain= par('vdb(vo)-idb(Is)') + phase= par('vp(vo)-ip(Is)').noise v(vo) Is 1 total equivalent input referred noise from 1k to 5g BER= 10 -12 =Q(I in,pp /2I n,in,rms )  I in,pp /2I n,in,rms =7 I inpp = 14 In,in,rms = Sensitivity

7.  Sensitivity = I inpp = 14 In,in,rms = 14* 0.264uA =3.7uA AC analysis Simulation result:

8. Example: 2.5Gb/s K28.5 pattern ---00111110101100000101-----.param h = 50u Iin 0 g1 pwl( +0.00ns h +0.20ns 0 0.800ns 0 +1.00ns h 2.800ns h +3.00ns 0 3.200ns 0 +3.40ns h 3.600ns h +3.80ns 0 4.000ns 0 +4.20ns h 4.800ns h +5.00ns 0 6.800ns 0 +7.00ns h 7.200ns h +7.40ns 0 7.600ns 0 +7.80ns h 8.000ns h +R 0) PRBS Pattern 0 0 1 1 1 …. Rise time and fall time are both half of the bit time. K28.5 contains five consecutive 1’s and five consecutive 0’s. “h” is the magnitude of the input signal. 0.4ns

9. Example:.param width_eye =1.6ns phase=0ns. probe tran TIME_1.25G=par('TIME+phase-int((TIME+phase)/width_eye)*width_eye') Eye Diagram Phase Width_eye X-Axis = TIME_1.25G

10. Jitter & Overload Measurement of Jitter : Overload: Increases the input level and then check the output signal in the eye diagram. Jitter (p-p) I in,pp = 3.7u,V out,pp = 5.1mV I in,pp = 370u, V out,pp = 0.52V I in,max = overload