1. A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Improved Effective Phase Resolution Chang-Kyung Seong 1), Seung-Woo Lee 2), and Woo-Young Choi 1) 1) Department of Electronic and Electrical Engineering Yonsei University 2) Switching Technology Team Electronics and Telecommunications Research Institute

2. High-Speed Circuits and Systems Lab. Yonsei Univ. Contents  Introduction  Conventional Dual-Loop CDR and Problems  Proposed Dual-Loop CDR  Simulation and Experimental Results  Chip summary  Conclusion

3. High-Speed Circuits and Systems Lab. Yonsei Univ. Introduction (1)  Multi-channel application (e.g. Switch)  Dozens ~ Hundreds of CDRs integrated in single die  Requirements for CDR  Small die area  Low power consumption  Robustness to noise coupled from adjacent blocks Switch Core Logics Tx / Rx for each channel Switch Core Logics

4. High-Speed Circuits and Systems Lab. Yonsei Univ. Introduction (2) CDR #1 Pad external reference clock Data#1 Data#2 Data#3 Data#4 Retimed Data #4 Recovered Clock #4 Retimed Data #3 Recovered Clock #3 Retimed Data #2 Recovered Clock #2 Retimed Data #1 Recovered Clock #1 Synthesized Reference Clock CDR #2 CDR #3 CDR #4 Ref. PLL  Dual-loop CDR  Shared Reference PLL  Each CDR cores using phase interpolator No jitter accumulation Digital control - no loop filter, robustness to noise

5. High-Speed Circuits and Systems Lab. Yonsei Univ. Conventional Digitally-Controlled Dual-Loop Structure Phase Controller Bang-Bang Phase Detector Phase Selection Phase Interpolator Multi-Phase Reference Clock from PLL Data in. PFDCP VCO LF /M External Reference Clock Ref. PLL CDR core Two Selected Phases

6. High-Speed Circuits and Systems Lab. Yonsei Univ. Reference Clock from PLL Conventional Digitally-Controlled Dual-Loop Structure Phase Controller Bang-Bang Phase Detector Phase Selection Phase Interpolator Data in. PFDCP VCO LF /M External Reference Clock Ref. PLL CDR core Two Selected Phases Phase Selection Phase Interpolator Phase Interpolated

7. High-Speed Circuits and Systems Lab. Yonsei Univ. Conventional Digitally-Controlled Dual-Loop Structure Retimed Data Recovered Clock UP/DN Phase Controller Bang-Bang Phase Detector Phase Selection Phase Interpolator Reference Clock from PLL Data in. PFDCP VCO LF /M External Reference Clock Ref. PLL CDR core Two Selected Phases Bang-Bang Phase Detector UP DN

8. High-Speed Circuits and Systems Lab. Yonsei Univ. Effect of Phase Resolution  Jitter Generation  Quantization error Digitally-Controlled CDR generates “discontinuous phase”  Jitter generation ∝ 1 / Phase Resolution Quantization error * M. H. Perrott, “Fast and accurate behavioral simulation of fractional-N synthesizers and other PLL/DLL circuits,” Design Automation Conference, pp.498-503, Jun. 2002.

9. High-Speed Circuits and Systems Lab. Yonsei Univ. Effect of Phase Resolution  Jitter Suppression and Frequency Offset Tracking  Higher (more fine) phase resolution Smaller phase steps Narrower Loop Bandwidth More jitter rejection and Slower offset tracking Phase resolution Jitter generation Jitter suppression Frequency offset tolerance ∴

10. High-Speed Circuits and Systems Lab. Yonsei Univ. Limit of Phase Resolution in Phase Interpolator  Two control methods  Binary-weighted code 2 N levels, Simple but Phase overshoot  Thermometer code N+1 levels, Complex but no Phase overshoot,where N = bit width of control word Difficult to increase phase resolution of PI higher than 16-level, or 4-bit. ∴

11. High-Speed Circuits and Systems Lab. Yonsei Univ. Design Goals  Achieving sufficiently high phase resolution with little additional power consumption and die area  By using only 4-phase reference clocks and 16- level thermometer coded PI

12. High-Speed Circuits and Systems Lab. Yonsei Univ. Proposed Structure  Digitally-Controlled Delay Buffer (DCDB) is inserted for higher phase resolution Phase Controller Bang-Bang Phase Detector Phase Interpolator Digitally-Controlled Delay Buffer Up/Down Filter 4-Phase Reference Clock from PLL Data in. Recovered Clock Retimed Data 2:1 MUX

13. High-Speed Circuits and Systems Lab. Yonsei Univ. Digitally-Controlled Delay Buffer  Current-starved inverter, or buffer  Linearly variable delay for control codes Digitally-Controlled Delay Buffer Control Code (2-bit) Input Clock Delayed Clock Input Clock Delayed Clock Adjacent interpolated phases

14. High-Speed Circuits and Systems Lab. Yonsei Univ. Digitally-Controlled Delay Buffer  Current-starved inverter, or buffer  Linearly variable delay for control codes Digitally-Controlled Delay Buffer Control Code (2-bit) Input Clock Delayed Clock Input Clock Delayed Clock Adjacent interpolated phases

15. High-Speed Circuits and Systems Lab. Yonsei Univ. Enhancement of Phase Resolution  4X higher phase resolution by combining PI and DCDB N total phase = N reference phase × N PI resolution × N DCDB resolution = 4-level × 16-level × 4-level = 256-level (8-bit) Interpolated phase Delayed phase Interpolated phases

16. High-Speed Circuits and Systems Lab. Yonsei Univ. Enhancement of Phase Resolution  4X higher phase resolution by combining PI and DCDB Interpolated phase Delayed phase N total phase = N reference phase × N PI resolution × N DCDB resolution = 4-level × 16-level × 4-level = 256-level (8-bit) Interpolated phases

17. High-Speed Circuits and Systems Lab. Yonsei Univ. Delay Error of DCDB Interpolated phase Delayed phase Interpolated phase Delayed phase  Negative error (shorter delay than desired one)  Positive error (longer delay than desired one)

18. High-Speed Circuits and Systems Lab. Yonsei Univ. Delay Error of DCDB Interpolated phase Delayed phase Interpolated phase Delayed phase  Negative error (shorter delay than desired one)  Positive error (longer delay than desired one)

19. High-Speed Circuits and Systems Lab. Yonsei Univ. Delay Error of DCDB Interpolated phase Delayed phase Interpolated phase Delayed phase  Negative error (Shorter delay than desired one)  Positive error (Longer delay than desired one)

20. High-Speed Circuits and Systems Lab. Yonsei Univ. Sensitivity - Jitter Generation vs. Delay Error of DCDB  Behavioral simulation - CPPSIM, Circuit-level simulation - HSPICE  Relatively flat jitter generation for wide range of DCDB error  Why?  Effect of enhanced phase resolution > Effect of locally wrong phase movements

21. High-Speed Circuits and Systems Lab. Yonsei Univ. Die Photo 255 ㎛ 165 ㎛

22. High-Speed Circuits and Systems Lab. Yonsei Univ. Experiment – Jitter vs. Delay error of DCDB DCDB error = -50%DCDB error = 0%DCDB error = +50%  Measured waveform of recovered clock at 200ppm frequency offset (-50%) (0%)(+50%)

23. High-Speed Circuits and Systems Lab. Yonsei Univ. Experiment - Jitter Suppression  2 7 -1 PRBS transmitted through 2m PCB trace and 3.5m cable.  In 200ppm frequency offset 114.3ps P-P 424ps RMS 38.89 ps P-P 212 ps RMS

24. High-Speed Circuits and Systems Lab. Yonsei Univ. Summary of Prototype Chip Process Supply Data Rate Offset Tolerance Power Consumption 0.18 ㎛ CMOS 17.8mW (CDR core) 2.0V 1.25-Gb/s ±400ppm Die Area (CDR core) 255×165 ㎛ 2

25. High-Speed Circuits and Systems Lab. Yonsei Univ. Conclusion  A novel method to enhance phase resolution is proposed.  By combining PI and DCDB, phase resolution can be enhanced with little additional power consumption and die area.  In both simulations and chip measurement, jitter performance is not sensitive to delay error of DCDB.

26. High-Speed Circuits and Systems Lab. Yonsei Univ. Thank You !!