1. A 2.9-30.3GHz Fourth-Harmonic Voltage-Controlled Oscillator in 130nm SiGe BiCMOS Technology Yang Lin and David E. Kotecki Electrical and Computer Engineering Department University of Maine, USA Dec.12-15, 2010 1 17th IEEE International Conference on Electronics, Circuits and Systems

2. Outline Voltage-controlled oscillator (VCO) Wide-tuning VCO applications Previous work on the state-of-the-art wide-tuning VCOs Design & Post-layout simulation of this work Dec.12-15, 2010 2 17th IEEE International Conference on Electronics, Circuits and Systems

3. Voltage-Controlled Oscillator (VCO) Dec.12-15, 2010 3 17th IEEE International Conference on Electronics, Circuits and Systems

4. Wide-tuning VCO applications Radar Broadband Communication Dec.12-15, 2010 4 17th IEEE International Conference on Electronics, Circuits and Systems Remote Sensing

5. State-of-the-art wide-tuning VCOs The widest tuning range in the 130nm ring VCOs reported Frequency (GHz) TopologyTechnology 1-9Two-stage VCOCMOS 130nm 1.82-10.18Two-stage digitally controlledCMOS 130nm 3-10Digitally-controlled ringCMOS 90nm 1-10Four-stage VCOCMOS 90nm 0.23-6.3Relaxation VCOCMOS 90nm 0.1-65.8Triple-push with lumped devices CMOS 90nm 3-11Coupled two-stageCMOS 180nm 1.25-13.66QVCO + two stages XORAlGaAs/GaAs 2.9-30.3QVCO + XOR + Push-push frequency doubler BiCMOS SiGe 130nm Dec.12-15, 2010 5 17th IEEE International Conference on Electronics, Circuits and Systems This work

6. Dec.12-15, 2010 6 17th IEEE International Conference on Electronics, Circuits and Systems  For the XOR, differential inputs Ap and An (0 o delay @ frequency f 0 ) XOR differential inputs Bp and Bn (90 o delay @ frequency f 0 ) = differential outputs Zp and Zn (frequency 2f 0 )  Base-collector-connected (level-shifting) NPN transistors: decrease the XOR input voltages for Bp and Bn Architecture

7. Ring Quadrature VCO (QVCO)  Gate width/length (µm)  Buffer: Common source (amplified output)  ‘Vctrl’ is high: low-frequency mode, T1 & T4 close to ‘off’, T2 & T3 provide most currents  ‘Vctrl’ achieves a specific high value, the oscillation freq. keeps the same  ‘Vctrl’ is low: high-frequency mode, |V gs | of T1 & T4 increases, current and freq. boost  Increasing ‘Vdd’ boosts the output frequency Dec.12-15, 2010 7 17th IEEE International Conference on Electronics, Circuits and Systems Delay cell

8. Dec.12-15, 2010 17th IEEE International Conference on Electronics, Circuits and Systems 8 BiCMOS Gilbert XOR  Logic part, Emitter followers & Current source  Delays of Ap, An, Bp and Bn are 0 o, 180 o, 90 o and 270 o  Bp & Bn are ~0.7V lower than Ap & An  Zp and Zn are differential outputs  BiCMOS XOR outperforms CMOS XOR: high freq. & differential outputs CMOS XOR: up to ~5.5GHz input freq. Emitter followers as buffers Current Source Logic Part ABA XOR B Ap<An(0)Bp<Bn(0)Zp<Zn(0) Ap<An(0)Bp>Bn(1)Zp>Zn(1) Ap>An(1)Bp<Bn(0)Zp>Zn(1) Ap>An(1)Bp>Bn(1)Zp<Zn(0)

9. Push-push frequency doubler Dec.12-15, 2010 9 17th IEEE International Conference on Electronics, Circuits and Systems for all x)( Half-circuit Half-circuit model Schematic L

10. Dec.12-15, 2010 17th IEEE International Conference on Electronics, Circuits and Systems 10 Doubled frequency dominates !! Zp & Zn out-of-phase: odd harmonics cancel, even harmonics add L Assuming Push-push frequency doubler (continued)

11. Microchip Layout Size: 750µm×500µm The ground & power planes are not shown for clarity. Dec.12-15, 2010 11 17th IEEE International Conference on Electronics, Circuits and Systems 500µm 750µm Vbuffer Vctrl Vdd! Vxor VL out Gnd! QVCO XOR Push-push frequency doubler

12. Post-layout simulation results Oscillation frequency Dec.12-15, 2010 12 17th IEEE International Conference on Electronics, Circuits and Systems 30.3GHz 2.9GHz Tuning range = 165%

13. VCO transient output at 30.3GHz (into a 50 Ω load) Non-ideal 4 th -harmonic output A small 2 nd -harmonic signal still exists due to the incomplete cancellation of Zp and Zn signals Peak-peak voltage amplitude ~20mV Dec.12-15, 2010 13 17th IEEE International Conference on Electronics, Circuits and Systems

14. 4 th -harmonic output power spectrum into a 50 Ω load 30.3 GHz, -33.5 dBm The rejections 23.5dB @7.575GHz 8dB @15.15GHz 12.5dB @22.725GHz @30.3 GHz, Dissipated power: 34.2 mW, Output power: -33.5 dBm @2.9 GHz, Dissipated power: 32.89 mW, Output power: -56.5 dBm Dec.12-15, 2010 14 17th IEEE International Conference on Electronics, Circuits and Systems

15. Phase Noise (PN) versus offset frequency At 10MHz offset frequency, PN= -86.04 dBc/Hz @ 30.3GHz oscillation frequency PN= -102.2 dBc/Hz @ 2.9GHz oscillation frequency Dec.12-15, 2010 15 17th IEEE International Conference on Electronics, Circuits and Systems 30.3GHz oscillation frequency, -86.04 dBc/Hz @10MHz offset frequency

16. Conclusions Dec.12-15, 2010 16 17th IEEE International Conference on Electronics, Circuits and Systems TopologyA ring QVCO + An XOR + A push-push frequency doubler PerformanceThe widest tuning range in the 130nm ring VCOs reported Tuning Range (GHz)2.9 to 30.3 (165%) Dissipated Power (mW)34.2 @ 30.3GHz, 32.89 @ 2.9GHz Output Power to a 50Ω load (dBm)-33.5 @ 30.3GHz, -56.5 @ 2.9GHz Phase noise @ 10MHz offset (dBc/Hz) -86.04 @ 30.3GHz, -102.2 @ 2.9GHz Microchip Area750µm×500µm

17. Thank you very much! Dec.12-15, 2010 17 17th IEEE International Conference on Electronics, Circuits and Systems