1. Sequential Circuits

2. Two primary differences between combinational circuits and sequential circuits –Sequential circuits are synchronous (use a clock) –Sequential circuits have memory (current state)

3. Clock A series of pulses –Sometimes referred to as a pulse train –Basically, it’s an digital signal just oscillates between 0 and 1 1 0 One period Rising edge Falling edge

4. Clock Clock period is specified in units of time –Seconds, milliseconds, microseconds… Clock frequency is specified in units of frequency – 1/period – pulses per time- unit –Hertz, Megahertz, Gigahertz…

5. Memory Devices Flip flops –Four basic types SR, D, JK, T –Each type stores 1-bit (two states: 0/1) –Each maintains its current state until a clock pulse arrives i.e. Ignores input lines until a clock pulse reaches the clock input

6. SR Flip-Flop “Set/Reset” –Two input lines –One clock input line –Two output lines S R C Q Q’ SRQ(t+1)Comments 00Q(t)No change 010Reset to 0 101Set to 1 11?Unspecified Clock symbol means that this flip-flop responds to the rising edge of a clock pulse Characteristic Table Q(t) refers to the current state Q(t+1) refers to the next state

7. D Flip-Flop “Delay” –One input line –One clock input line –Two output lines D C Q Q’ DQ(t+1)Comments 00Clear to 0 11Set to 1 Clock symbol means that this flip-flop responds to the rising edge of a clock pulse Characteristic Table Q(t+1) refers to the next state

8. JK Flip-Flop “JK” –Two input lines –One clock input line –Two output lines J K C Q Q’ JKQ(t+1)Comments 00Q(t)No change 010Reset to 0 101Set to 1 11Q’(t)Complemen t Clock symbol means that this flip-flop responds to the rising edge of a clock pulse Characteristic Table Q(t) refers to the current state Q(t+1) refers to the next state

9. T Flip-Flop “Toggle” –One input line –One clock input line –Two output lines T C Q Q’ TQ(t+1)Comments 0Q(t)No change 1Q’(t)Complemen t Clock symbol means that this flip-flop responds to the rising edge of a clock pulse Characteristic Table Q(t+1) refers to the next state

10. Edge-Triggering Output of the flip-flop occurs on the edge of a pulse –Rising edge (0 to 1 transition) –Falling edge (1 to 0 transition) Clock symbol means that this flip-flop responds to the rising edge of a clock pulse Clock symbol means that this flip-flop responds to the falling edge of a clock pulse

11. Edge-Triggering 1 0 positive clock transition output frozen Positive (rising) edge-triggered 1 0 negative clock transitionoutput frozen Negative (falling) edge-triggered

12. Edge-Triggering Setup time –This is the minimum time that the inputs must remain constant before the edge transition Hold time –This is the amount of time in which the inputs must not change after the edge transition These values are not to interesting from a theoretical point of view but can make or break a circuit in practice

13. Master-Slave Flip-Flops Two flip-flops of the same type wired together –Master Rising edge triggered Receives inputs from “outside world” Sends outputs to the slave –Slave is falling edge triggered Falling edge triggered Receives inputs from master Sends outputs to the “outside world” This set-up basically creates a more stable flip-flop in terms of set-up and hold times

14. Master-Slave JK Flip-Flop J K C Q Q’ J K C Q MasterSlave Don’t be overly concerned with this configuration!

15. Additional Inputs May have… –Preset and Clear inputs which are used to set the flip flop to a predetermined state prior to starting the clock –Initialization

16. Excitation Tables In performing circuit design using flip- flops we often know the state transition Q(t) → Q(t+1) and need to find the appropriate input values To do so we use an excitation table It’s basically the reverse of the characteristic table

17. Flip-Flop Excitation Tables SR flip-flop Q(t)Q(t+1)SR 000x 0110 1001 11x0 D flip-flop Q(t)Q(t+1)D 000 011 100 111 JK flip-flop Q(t)Q(t+1)JK 000x 011x 10x1 11x0 T flip-flop Q(t)Q(t+1)T 000 011 101 110 x – don’t care input value

18. Sequential Circuits Combination of logic gates, flip-flops (memory elements), and a clock signal The circuit can be described in two parts –The combinational part –The sequential part

19. The Combinational Part Nothing more than what we’ve been doing so far –Describe outputs in terms of logic gates and flip-flop outputs

20. The Sequential Part Flip-flop input equations –Describe the inputs to flip-flop elements in terms of logic gates and flip-flop elements

21. clock x A A’ B B’ y Consider The Circuit DBDB DADA Input(s) Output(s) Flip-flop Input(s)

22. Describe The Circuit Flip-flop input equations: –D A = Ax + Bx –D B = A’x –Note that the input(s) to the flip-flop also determines its next-state based on its characteristic table Output equation –y = Ax’ + Bx’

23. State Table Sequential circuits are described in terms of time –Since they have a memory and a clock –At any give time (relative to the clock) we can describe the internal state (values in flip-flops) of a sequential circuit The state table describes outputs and next states as functions of inputs and current states –It’s nothing more than a truth table

24. State Table Present State (time t) InputNext State (time t+1) Output ABxDADA DBDB y 000000 001010 010001 011110 100001 101100 110001 111100 D A = Ax + Bx D B = A’x Flip-flop Equation(s) y = Ax’ + Bx’ Output Equation(s) State Table

25. State Diagram Graphical representation of the state table –States are represented by circles Value inside the circle represents the contents of flip-flops –Transitions between states are represented by arcs between circles Values on the arcs represent the inputs that cause the transition and, possibly, the outputs as a result of the transition

26. State Diagram 0/0 0/1 1/0 0/1 1/0

27. State Tables/Diagrams Represent the same information Are derivable from one another They exist solely to support design and understanding of sequential circuit behavior One form may be more suitable for a given task than the other

28. Designing a Circuit The goal of circuit design is to convert a specification (a bunch of words) into a circuit –No different than software development! Consider this example from the book –Design a circuit that counts modulo 4 every time it receives a 1 on the input line

29. State Diagram X = 0 X = 1

30. State Table Present State (time t) InputNext State (time t+1) ABxAB 00000 00101 01001 01110 10010 10111 11011 11100

31. Flip-Flop Usage We know we need 2 flip-flops since the counter must count modulo 4 (2 bits) We can choose any type we want –D, T, SR, JK –By looking at the excitation table for the chosen type we can create flip-flop equations

32. JK Flip-Flop Based Design Present State (time t) InputNext State (time t+1) Flip-Flop Inputs ABxABJAJA KAKA JBJB KBKB 000000x0x 001010x1x 010010xx0 011101xx1 10010x00x 10111x01x 11011x0x0 11100x1x1 JK flip-flop Q(t)Q(t+1)JK 000x 011x 10x1 11x0 JK Excitation Table State Table Excitation Table

33. Simplification Need to specify combination circuits for –J A input –K A input –J B input –K B input Use 3-variable K-maps –One for each required input –Map/simplify the “Flip-Flop Input” columns of the table

34. K-Map Simplification 00011110 00010 1xxxx 00011110 001xx 101xx 00011110 0xx10 1xx10 00011110 0xxxx 10010 A BxBx A BxBx A BxBx A BxBx JAJA KAKA JBJB KBKB

35. Draw The Logic Gates A B x clock

36. Homework Pages 37-38 –Problems 1-8, 1-9, 1-10, 1-11, 1-12, 1-13, 1-15, 1-16 Due next lecture

37. Exam #1 Chapters 1 and 3 –Binary number representations –2’s complement arithmetic –Boolean logic Axioms K-maps –Flip-flops State tables, state diagrams –Circuit design Closed book, closed notes – I’ll give you all you need