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© 2003-2008 BYU 18 ASYNCH Page 1 ECEn 224 Handling Asynchronous Inputs.

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Presentation on theme: "© 2003-2008 BYU 18 ASYNCH Page 1 ECEn 224 Handling Asynchronous Inputs."— Presentation transcript:

1 © 2003-2008 BYU 18 ASYNCH Page 1 ECEn 224 Handling Asynchronous Inputs

2 © 2003-2008 BYU 18 ASYNCH Page 2 ECEn 224 Asynchronous Signals Definition: A signal that can change at any time with respect to the clock. Examples: –Push buttons –Keystrokes –Digital signals from different clock domain

3 © 2003-2008 BYU 18 ASYNCH Page 3 ECEn 224 Two Problems with Asynchronous Inputs 1.Flip flops could become metastable 2.State machines may transition to incorrect next state These are two independent problems.

4 © 2003-2008 BYU 18 ASYNCH Page 4 ECEn 224 Problem #1 Metastability

5 © 2003-2008 BYU 18 ASYNCH Page 5 ECEn 224 Asynchronous Signals Problem: Asynchronous signals do not always respect setup and hold times –Asynchronous signals may change at any time Clock t setup t hold ok bad

6 © 2003-2008 BYU 18 ASYNCH Page 6 ECEn 224 Metastability S=0 R=0 Q=1 Q’=0 Imagine if R is pulsed high for a very short time then goes back low… –Could it impart just enough energy to get Q halfway between ‘1’ and ‘0’? –Latch might hang at the midway point for some time Could be a short time, could be a long time –This is called metastability

7 © 2003-2008 BYU 18 ASYNCH Page 7 ECEn 224 Metastability Violating t setup for a D flip flop can cause very short pulses on signals Y and Z, and make flip flop metastable D CLK Q Q’ Y Z

8 © 2003-2008 BYU 18 ASYNCH Page 8 ECEn 224 Metastability Once a flip flop goes metastable, it is impossible to bound how long it will remain there Analogy: Roll ball up roof just hard enough to get it to balance on top…

9 © 2003-2008 BYU 18 ASYNCH Page 9 ECEn 224 Metastability Once a flip flop goes metastable, it is impossible to bound how long it will remain there Analogy: Roll ball up roof just hard enough to get it to balance on top… When will it come down?

10 © 2003-2008 BYU 18 ASYNCH Page 10 ECEn 224 Probability of Metastability The probability of an asynchronous signal causing metastability in a given clock cycle is very low However, there are millions or even billions of clock cycles every second Mean Time Between Failure (MTBF) quantifies how often a flip flop with an asynchronous input is likely to go metastable MTBF depends on: –Flip flop’s clock frequency –Frequency of changes on the asynchronous input –Electrical characteristics of the flop flop Typical MTBF numbers can range from minutes for high frequency systems to thousands of years for slower devices

11 © 2003-2008 BYU 18 ASYNCH Page 11 ECEn 224 Metastability Solutions Solution #1: Specially-designed flip flops that are particularly resistant (hardened ) Solution #2: Multiple FF’s in series increases resistance to metastability –At the expense of response time D Q AsynchronousInSynchronizedOut Could also be hardened flip flops

12 © 2003-2008 BYU 18 ASYNCH Page 12 ECEn 224 Problem #2 May Lead to Wrong Next State (No metastability involved here…)

13 © 2003-2008 BYU 18 ASYNCH Page 13 ECEn 224 Wrong Next State Asynchronous inputs might cause the wrong next state to be loaded Two possible causes: –Unequal logic path lengths (Cause A) –False outputs on IFL outputs (Cause B)

14 © 2003-2008 BYU 18 ASYNCH Page 14 ECEn 224 D Q IFL A 11 A A’ 00 N0 N1 C0 C1 5ns10ns clk Cause A: Unequal Path Lengths

15 © 2003-2008 BYU 18 ASYNCH Page 15 ECEn 224 D Q IFL A=0 11 A A’ 00 N0=0 N1=0 Q0=0 Q1=0 5ns10ns clk Time t = 12 ns Cause A: Unequal Path Lengths

16 © 2003-2008 BYU 18 ASYNCH Page 16 ECEn 224 Cause A: Unequal Path Lengths D Q IFL A1A1 11 A A’ 00 5ns10ns Time t = 13 ns N0=0 N1=0 Q0=0 Q1=0 clk

17 © 2003-2008 BYU 18 ASYNCH Page 17 ECEn 224 Cause A: Unequal Path Lengths D Q IFL A1A1 11 A A’ 00 5ns10ns Time t = 18 ns N0=0 N1  1 Q0=0 Q1=0 clk

18 © 2003-2008 BYU 18 ASYNCH Page 18 ECEn 224 Cause A: Unequal Path Lengths D Q IFL A1A1 11 A A’ 00 5ns10ns Time t = 20 ns (clock rises) N0=0 N1  1 Q0=0 Q1  1 clk

19 © 2003-2008 BYU 18 ASYNCH Page 19 ECEn 224 CLK Current State 0010 A N1 N0 5ns 10ns Wrong next state!! Erroneous State Transition 11 A A’ 00 05102530

20 © 2003-2008 BYU 18 ASYNCH Page 20 ECEn 224 CLK Current State 0010 A N1 N0 5ns 10ns Erroneous State Transition 11 A A’ 00 05102530 Danger period

21 © 2003-2008 BYU 18 ASYNCH Page 21 ECEn 224 Solution #1: Synchronize Signal A D Q IFL A N0 N1 C0 C1 5ns10ns clk D Q clk IFL now sees synchronous input Synchronizing flip flop is still susceptible to metastability due to setup time violations. But that is a different problem with previously-seen solutions.

22 © 2003-2008 BYU 18 ASYNCH Page 22 ECEn 224 Solution #2: Use Gray Codes for States D Q IFL A 11 A A’ 00 N0 N1 C0 C1 5ns10ns clk 11 A A’ 01 Will never have case when both paths transitioning… State change will occur or it won’t…

23 © 2003-2008 BYU 18 ASYNCH Page 23 ECEn 224 Cause B: False Outputs Gray coding state transitions doesn’t always work! We can still have false outputs on our input forming logic These hazards can also lead to incorrect transitions

24 © 2003-2008 BYU 18 ASYNCH Page 24 ECEn 224 F = A’B + AC F A’ B A C Logic Hazards This is the conventional K-map solution Asynchronous input A

25 © 2003-2008 BYU 18 ASYNCH Page 25 ECEn 224 Gates Have Real Timing… A g1 g2 F Called a false output F A’ B=1 A C=1 g1 g2

26 © 2003-2008 BYU 18 ASYNCH Page 26 ECEn 224 Gates Have Real Timing… A g1 g2 F If the clock edge occurs here… you’re toast! F A’ B=1 A C=1 g1 g2

27 © 2003-2008 BYU 18 ASYNCH Page 27 ECEn 224 Hazard-Free Logic Design Make sure all adjacent 1’s are covered by the same prime implicant –Add redundant prime implicants as needed Redundant but will eliminate false output F A’ B A C B C g1 g2 g3 On ABC = ‘111’ to ABC = ‘011’, g3 will hold F high entire time.

28 © 2003-2008 BYU 18 ASYNCH Page 28 ECEn 224 No False Output… A g1 g2 g3 F F A’ B=1 A C=1 B=1 C=1 g1 g2 g3

29 © 2003-2008 BYU 18 ASYNCH Page 29 ECEn 224 Solution #3 Use both gray code states and hazard-free logic minimization –Gray code encoding ensure only one state bit changes Solves the unequal path problem –HFLM ensures no hazards (false outputs) exist on input forming logic 1 S 0101 S’ D Q IFL A N0 N1 C0 C1 5ns 10ns clk

30 © 2003-2008 BYU 18 ASYNCH Page 30 ECEn 224 Asynchronous Input Problem Summary Problem #1: Asynchronous inputs can cause flip flops to enter a metastable state Problem #2: Asynchronous inputs can cause invalid state transitions A) Different propagation delays on IFL paths to different state bits B) False outputs on IFL outputs

31 © 2003-2008 BYU 18 ASYNCH Page 31 ECEn 224 Solutions Summary Metastability –Solution #1: Use hardened flip flops May not be available –Solution #2: Add flip flops in series to decrease susceptibility Latency may cause problems, if we need to react immediately Invalid State Transitions –Solution #1: Synchronize asynchronous inputs with a flip flop Simplest solution Latency may cause problems, if we need to react immediately –Solution #2: gray code state encoding (doesn’t always work) –Solution #3: gray code + hazard-free IFL Takes extra hardware May require additional states to get gray code transitions Use when need to react quickly to input FF’s still susceptible to metastability HFLM only works for single-input changes The same solution!

32 © 2003-2008 BYU 18 ASYNCH Page 32 ECEn 224 Other Asynchronous Input Issues

33 © 2003-2008 BYU 18 ASYNCH Page 33 ECEn 224 Multiple Asynchronous Inputs What if we have a state transition that depends on multiple asynchronous inputs? S1 A’B A’B’ S0 S2 A

34 © 2003-2008 BYU 18 ASYNCH Page 34 ECEn 224 Multiple Asynchronous Inputs Break up the states so that only one transition is dependant on each input S1 A’ S0 S2 A S3 B S1 A’B A’B’ S0 S2 A B’

35 © 2003-2008 BYU 18 ASYNCH Page 35 ECEn 224 Multiple Clock Systems When you make up the rules –You can cheat… In this class we cheat: –One global clock  simplifies our work In the real world: –Systems have multiple clocks

36 © 2003-2008 BYU 18 ASYNCH Page 36 ECEn 224 Multi-clock System This is a PCI Express board that plugs into a computer’s motherboard RAM (DDR SDRAM) FPGA PCI-E Interface (PHY) Video DAC PCI-E Connector

37 © 2003-2008 BYU 18 ASYNCH Page 37 ECEn 224 Multi-clock System This is a PCI Express board that plugs into a computer’s motherboard 100 MHz 200 MHz 25.175 MHz 250 MHz 2.5 GHz How do they talk to each other?

38 © 2003-2008 BYU 18 ASYNCH Page 38 ECEn 224 Multi-Clock System This is a PCI card, plugs into a PC. Let’s use it to do a PhotoShop Accelerator… Xilinx FPGA RAM PCI Bus Interface Circuit Clocked @ 150MHz Clocked @ 66MHz

39 © 2003-2008 BYU 18 ASYNCH Page 39 ECEn 224 Multi-Clock Systems This system has multiple clock domains Signals that cross domains look like asynchronous signals to the other domain For simple control signals, we can use one of the methods discussed in this lecture –Synchronizing flip flops –Hazard free logic + gray codes When data transfer is involved, the required solutions are more complicated (ECEn 320)

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