1. © Digital Integrated Circuits 2nd Interconnect Digital Integrated Circuits A Design Perspective Coping with Interconnect Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Revised from Digital Integrated Circuits, © Jan M. Rabaey

2. © Digital Integrated Circuits 2nd Interconnect Impact of Interconnect Parasitics Reduce Robustness Affect Performance Increase delay Increase power dissipation Classes of Parasitics Capacitive Resistive Inductive

3. © Digital Integrated Circuits 2nd Interconnect INTERCONNECT

4. © Digital Integrated Circuits 2nd Interconnect Capacitive Cross Talk

5. © Digital Integrated Circuits 2nd Interconnect Capacitive Cross Talk Dynamic Node 3 x 1  m overlap: 0.19 V disturbance C Y C XY V DD PDN CLK In 1 2 3 Y X 2.5 V 0 V A non-related signal Y is routed in Metal 1 wire over the polysilicon gate of the inverter gate. Assume that C Y =6fF and C XY = (3*1*0.057+ 2*3*0.054)=0.5fF Combined with charge redistribution and clock- feed through effects, this might cause circuit failure.

6. © Digital Integrated Circuits 2nd Interconnect Wiring Capacitances (0.25  m CMOS) Rows represent the top plate, columns the bottom plate. Shaded row for fringing capacitance in aF/µm, unshaded for parallel plate capacitance (area capacitance) in aF/µm^2 smaller 40 95 85 115

7. © Digital Integrated Circuits 2nd Interconnect Capacitive Cross Talk: Driven Node  XY = R Y (C XY +C Y ) If the rise time is comparable or larger than the time constant, the peak value of disturbance is diminished. So we need to Keep time-constant smaller than rise time, that is to decrease either capacitance or resistance (keeper transistor in dynamic design). V (Volt) 0 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 10.80.6 t (nsec) 0.40.2 X Y V X R Y C XY C Y tr↑tr↑

8. © Digital Integrated Circuits 2nd Interconnect Dealing with Capacitive Cross Talk  Avoid floating nodes  Protect sensitive nodes  Make rise and fall times as large as possible (*?)  Do not run wires together for a long distance  Use shielding wires  Use shielding layers

9. © Digital Integrated Circuits 2nd Interconnect Shielding GND Shielding wire Substrate (GND) Shielding layer V DD Interleave every signal layer with a GND or VDD metal plane

10. © Digital Integrated Circuits 2nd Interconnect Cross Talk and Performance CcCc - When neighboring lines switch in opposite direction of victim line, delay increases DELAY DEPENDENT UPON ACTIVITY IN NEIGHBORING WIRES Miller Effect - Both terminals of capacitor are switched in opposite directions (0  V dd, V dd  0), Miller Effect - Effective voltage is doubled and additional charge is needed (from Q=CV)

11. © Digital Integrated Circuits 2nd Interconnect Impact of Cross Talk on Delay r is ratio between capacitance to neighbor and to GND Activity on bus of different bits

12. © Digital Integrated Circuits 2nd Interconnect Encoding Data Avoids Worst-Case Conditions Encoder Decoder Bus In Out It is possible to encode the data in such a way that the transitions that “victimize” delay are eliminated. This requires that the bus interface units include encode/decoder functions.

13. © Digital Integrated Circuits 2nd Interconnect Structured Predictable Interconnect Example: Dense Wire Fabric ([Sunil Kathri]) Trade-off: Cross-coupling capacitance 40x lower, 2% delay variation Increase in area and overall capacitance Also widely used in FPGAs V: VDDS: signalG: GND

14. © Digital Integrated Circuits 2nd Interconnect Interconnect Projections Low-k dielectrics  Both delay and power are reduced by dropping interconnect capacitance  Types of low-k materials include: inorganic (SiO 2 ), organic (Polyimides) and aerogels (ultra low-k)  The numbers below are on the conservative side of the NRTS roadmap 

15. © Digital Integrated Circuits 2nd Interconnect Driving Large Capacitances V in V out C L V DD Transistor Sizing Cascaded Buffers

16. © Digital Integrated Circuits 2nd Interconnect Using Cascaded Buffers C L = 20 pF InOut 12N 0.25  m process C in = 2.5 fF t p 0 = 30 ps F = C L /C in = 8000 f opt = 3.6 N = 7 t p = 0.76 ns (See Chapter 5)

17. © Digital Integrated Circuits 2nd Interconnect Delay as a Function of F and N 10 1357 Number of buffer stages N 911 10,000 1000 100 t p / t p 0 F = F = 1000 F = 10,000 t p /t p0

18. © Digital Integrated Circuits 2nd Interconnect Output Driver Design Trade off Performance for Area and Energy Given t pmax find N and f  Area  Energy To a first order analysis, this simply says that small sizing factor f causes large area and power consumption!!!

19. © Digital Integrated Circuits 2nd Interconnect Output Driver Design: design for right speed Transistor Sizes for optimally-sized cascaded buffer t p = 0.76 ns Transistor Sizes of redesigned cascaded buffer t p = 1.8 ns 0.25  m process, C L = 20 pF Overall area of the later solution is 7 times smaller compared to the first one, while delay is increased by a factor of 2. Also, overall power dissipation of the load and buffer is reduced by 24%. f opt = 3.6 f d = 20

20. © Digital Integrated Circuits 2nd Interconnect How to Design Large Transistors G(ate) S(ource) D(rain) Multiple Contacts small transistors in parallel Reduces diffusion capacitance Reduces gate resistance

21. © Digital Integrated Circuits 2nd Interconnect Bonding Pad Design Bonding Pad Out In V DD GND 100  m GND Out Guard ring

22. © Digital Integrated Circuits 2nd Interconnect Guard ring  Guard rings are grounded p+ diffusions in a p-well and supply-connected n+ diffusions in an n-well that are used to collect injected minority carriers before they reach the base of the parasitic bipolar transistors.  They should be used surrounding the NMOS/PMOS transistors in the final stage of the output pad driver.  Used a lot in analog VLSI design.

23. © Digital Integrated Circuits 2nd Interconnect Chip Packaging Bond wires (~25  m) are used to connect the package to the chip Pads are arranged in a frame around the chip Pads are relatively large (~100  m in 0.25  m technology) Many chips areas are ‘pad limited’

24. © Digital Integrated Circuits 2nd Interconnect Pad Frame LayoutDie Photo

25. © Digital Integrated Circuits 2nd Interconnect Tristate Buffers  Most of the driver circuits have been simple inverters.  Tristate buffers is a variant. Suppose that one device is sending information on the bus, all other transmitting devices should be disconnected from the bus. This can be achieved by putting the output buffers of those devices in an high-impedance state Z that effectively disconnects the gate from the output wire.

26. © Digital Integrated Circuits 2nd Interconnect Tristate Buffers In En V DD Out Out = In.En + Z.En V DD In En Out Increased output drive

27. © Digital Integrated Circuits 2nd Interconnect INTERCONNECT

28. © Digital Integrated Circuits 2nd Interconnect Impact of Resistance  Impact of resistance is commonly seen in power supply distribution:  IR drop  Voltage variations  Delay increases  Power supply is distributed to minimize the IR drop and the change in current due to switching of gates

29. © Digital Integrated Circuits 2nd Interconnect IR Introduced Noise M 1 X I R 9 R Δ V f pre Δ V V DD V -Δ V I Ohmic voltage drop on the supply rails reduces the noise margins A 2cm long, 1 µm wide Vdd or Gnd wire with 1mA current and sheet resistance of 0.05 Ohm/□ gives a voltage drop of 1V.

30. © Digital Integrated Circuits 2nd Interconnect Power Distribution  Low-level distribution is in Metal 1  Power is ‘strapped’ in higher layers of metal.  The spacing is set by IR drop, electromigration, inductive effects  Always use multiple contacts on straps

31. © Digital Integrated Circuits 2nd Interconnect Power and Ground Distribution

32. © Digital Integrated Circuits 2nd Interconnect 3 Metal Layer Approach (EV4) 3rd “thick” metal layer added to the technology for EV4 design Power supplied from two sides of the die via 3rd metal layer 2nd metal layer used to form power grid 90% of 3rd metal layer used for power/clock routing Metal 3 Metal 2 Metal 1 Courtesy Compaq

33. © Digital Integrated Circuits 2nd Interconnect 4 Metal Layers Approach (EV5) 4th “thick” metal layer added to the technology for EV5 design Power supplied from four sides of the die Grid strapping done all in metal 90% of 3rd and 4th metals used for power/clock routing Metal 3 Metal 2 Metal 1 Metal 4 Courtesy Compaq

34. © Digital Integrated Circuits 2nd Interconnect 2 reference plane metal layers added to the technology for EV6 design Solid planes dedicated to Vdd/Vss Significantly lowers resistance of grid Lowers on-chip inductance 6 Metal Layer Approach – EV6 Metal 4 Metal 2 Metal 1 RP2/Vdd RP1/Vss Metal 3 Courtesy Compaq

35. © Digital Integrated Circuits 2nd Interconnect

36. © Digital Integrated Circuits 2nd Interconnect Resistance and the Power Distribution Problem: sizing Source: Cadence Requires fast and accurate peak current prediction Requires fast and accurate peak current prediction Heavily influenced by packaging technology Heavily influenced by packaging technology BeforeAfter

37. © Digital Integrated Circuits 2nd Interconnect Electromigration (1) The current density in a metal wire is limited due to an effect called electromigration, which eventually causes the wire to break or to short-circuit to another wire. Line open failure

38. © Digital Integrated Circuits 2nd Interconnect Electromigration (2) Open failure in contact Average current density and temperature are two main factors

39. © Digital Integrated Circuits 2nd Interconnect Resistivity and Performance Diffused signal propagation Delay ~ L 2 C N-1 CNCN C2C2 R1R1 R2R2 C1C1 TrTr V in R N-1 R N The distributed rc-line

40. © Digital Integrated Circuits 2nd Interconnect Driving an RC-line

41. © Digital Integrated Circuits 2nd Interconnect The Global Wire Problem Challenges  No further improvements to be expected after the introduction of Copper (superconducting, optical?)  Design solutions  Use of fat wires  Insert repeaters — but might become prohibitive (power, area)  Efficient chip floorplanning  Towards “communication-based” design  How to deal with latency?  Is synchronicity an absolute necessity?

42. © Digital Integrated Circuits 2nd Interconnect Interconnect Projections: Copper  Copper is planned in full sub-0.25  m process flows and large-scale designs (IBM, Motorola, IEDM97)  Cu ~ 2.2  -cm vs. 3.5 for Al(Cu)  40% reduction in resistance  Electromigration improvement; 100X longer lifetime (IBM, IEDM97)  Electromigration is a limiting factor beyond 0.18  m if Al is used (HP, IEDM95) Vias

43. © Digital Integrated Circuits 2nd Interconnect Interconnect: # of Wiring Layers # of metal layers is steadily increasing due to: Increasing die size and device count: we need more wires and longer wires to connect everything Rising need for a hierarchical wiring network; local wires with high density and global wires with low RC 0.25  m wiring stack

44. © Digital Integrated Circuits 2nd Interconnect Diagonal Wiring y x destination Manhattan source diagonal 20+% Interconnect length reduction Clock speed Signal integrity Power integrity 15+% Smaller chips plus 30+% via reduction Courtesy Cadence X-initiative The main problem is that incorporating diagonal design in Design Automation tools is harder

45. © Digital Integrated Circuits 2nd Interconnect Reducing RC-delay Repeater Optimal number of wire segments for a long wire! L crit =L / M AS inverter chain, the optimum is achieved when the delay of each wire segment is equal to that of a repeater!

46. © Digital Integrated Circuits 2nd Interconnect Wire pipelining Reg- ister Reg- ister Reg- ister clk Even with repeater, wire delay may still be larger than the clock cycle To accommodate this delay with GHz clock, wire pipelining techniques can be used

47. © Digital Integrated Circuits 2nd Interconnect Delay in Transmission Gate Networks

48. © Digital Integrated Circuits 2nd Interconnect Delay Optimization

49. © Digital Integrated Circuits 2nd Interconnect Resistivity and Performance  The signal delay in interconnect has been dominated by RC if the signal frequency is not too high.  In modern design, average length of global wires has been increasing.  At the same time, the average delay of individual gate goes down (since parasitics reduces).  This leads to a strange situation that it may take multiple clock cycles to transport a global signal to long distance.  Accurate synchronization becomes a big challenge (the timing issues we discussed before).