1. © Digital Integrated Circuits 2nd Interconnect ECE 558/658 : Lecture 20 Interconnect Design (Chapter 9) Clock distribution (Chapter 10.3.3) Atul Maheshwari

2. © Digital Integrated Circuits 2nd Interconnect The Wire – Chapter 4 – Lecture 15 schematics physical

3. © Digital Integrated Circuits 2nd Interconnect Capacitance: The Parallel Plate Model

4. © Digital Integrated Circuits 2nd Interconnect Fringing Capacitance

5. © Digital Integrated Circuits 2nd Interconnect Complete Capacitance Picture

6. © Digital Integrated Circuits 2nd Interconnect Wire Resistance

7. © Digital Integrated Circuits 2nd Interconnect Impact of Interconnect Parasitics Reduce Robustness Affect Performance Increase delay Increase power dissipation Classes of Parasitics Capacitive Resistive Inductive Impact of Parasitics

8. © Digital Integrated Circuits 2nd Interconnect INTERCONNECT

9. © Digital Integrated Circuits 2nd Interconnect Capacitive Cross Talk

10. © Digital Integrated Circuits 2nd Interconnect Capacitive Cross Talk Dynamic Node 3 x 1  m overlap: 0.19 V disturbance C Y C XY V DD PDN CLK In 1 2 3 Y X 2.5 V 0 V

11. © Digital Integrated Circuits 2nd Interconnect Capacitive Cross Talk Driven Node  XY = R Y (C XY +C Y ) Keep time-constant smaller than rise time V (Volt) 0 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 10.80.6 t (nsec) 0.40.2 X Y V X R Y C XY C Y tr↑tr↑

12. © Digital Integrated Circuits 2nd Interconnect Dealing with Capacitive Cross Talk  Avoid floating nodes  Protect sensitive nodes  Make rise and fall times as large as possible  Differential signaling  Do not run wires together for a long distance  Use shielding wires  Use shielding layers

13. © Digital Integrated Circuits 2nd Interconnect Shielding GND Shielding wire Substrate (GND) Shielding layer V DD

14. © Digital Integrated Circuits 2nd Interconnect Cross Talk and Performance CcCc - When neighboring lines switch in opposite direction of victim line, delay increases DELAY DEPENDENT UPON ACTIVITY IN NEIGHBORING WIRES Miller Effect - Both terminals of capacitor are switched in opposite directions (0  V dd, V dd  0) - Effective voltage is doubled and additional charge is needed (from Q=CV)

15. © Digital Integrated Circuits 2nd Interconnect Impact of Cross Talk on Delay r is ratio between capacitance to GND and to neighbor

16. © Digital Integrated Circuits 2nd Interconnect Structured Predictable Interconnect Example: Dense Wire Fabric ([Sunil Kathri]) Trade-off: Cross-coupling capacitance 40x lower, 2% delay variation Increase in area and overall capacitance

17. © Digital Integrated Circuits 2nd Interconnect Encoding Data Avoids Worst-Case Conditions Encoder Decoder Bus In Out

18. © Digital Integrated Circuits 2nd Interconnect Driving Large Capacitances V in V out C L V DD Transistor Sizing Cascaded Buffers

19. © Digital Integrated Circuits 2nd Interconnect Using Cascaded Buffers C L = 20 pF InOut 12N 0.25  m process Cin = 2.5 fF tp 0 = 30 ps F = CL/Cin = 8000 fopt = 3.6 N = 7 tp = 0.76 ns (See Chapter 5)

20. © Digital Integrated Circuits 2nd Interconnect How to Design Large Transistors G(ate) S(ource) D(rain) Multiple Contacts small transistors in parallel Reduces diffusion capacitance Reduces gate resistance

21. © Digital Integrated Circuits 2nd Interconnect Bonding Pad Design Bonding Pad Out In V DD GND 100  m GND Out

22. © Digital Integrated Circuits 2nd Interconnect Tristate Buffers In En V DD Out Out = In.En + Z.En V DD In En Out Increased output drive

23. © Digital Integrated Circuits 2nd Interconnect INTERCONNECT

24. © Digital Integrated Circuits 2nd Interconnect Impact of Resistance  Impact on performance - We have already learned how to drive RC interconnect  Impact of resistance is commonly seen in power supply distribution:  IR drop  Voltage variations  Power supply is distributed to minimize the IR drop and the change in current due to switching of gates

25. © Digital Integrated Circuits 2nd Interconnect Using Bypasses Driver Polysilicon word line Metal word line Metal bypass Driving a word line from both sides Using a metal bypass WL Kcells

26. © Digital Integrated Circuits 2nd Interconnect Resistivity and Performance Diffused signal propagation Delay ~ RC Delay ~ L 2 C N-1 CNCN C2C2 R1R1 R2R2 C1C1 TrTr V in R N-1 R N The distributed rc-line

27. © Digital Integrated Circuits 2nd Interconnect Repeaters  Repeaters are buffers / inverters inserted at regular intervals.  Makes Delay linearly proportional to the wire length.  Questions to be answered – Where and how big the repeaters should be ?

28. © Digital Integrated Circuits 2nd Interconnect Reducing RC-delay – Repeater insertion Repeater (chapter 5)

29. © Digital Integrated Circuits 2nd Interconnect Repeater Insertion Taking the repeater loading into account For a given technology and a given interconnect layer, there exists an optimal length of the wire segments between repeaters. The delay of these wire segments is independent of the routing layer!

30. © Digital Integrated Circuits 2nd Interconnect Repeater Design Limitations  Delay-optimal repeaters are area and power hungry – use of sub-optimal insertion  Optimal placement requires accurate modeling of interconnect.  Optimal placement not always possible.  Performance limited due to significant interconnect resistance.  Source of noise – Supply and Substrate

31. © Digital Integrated Circuits 2nd Interconnect Advanced techniques - Reducing the swing  Reducing the swing potentially yields linear reduction in delay  Also results in reduction in power dissipation  Delay penalty is paid by the receiver  Requires use of “sense amplifier” to restore signal level  Frequently designed differentially (e.g. LVDS)

32. © Digital Integrated Circuits 2nd Interconnect Single-Ended Static Driver and Receiver

33. © Digital Integrated Circuits 2nd Interconnect Dynamic Reduced Swing Network f In 2. f 1. f M 2 M 1 M 3 M 4 C bus C out BusOut V DD V V(Volt) f V bus V asym V sym 246 time (ns) 810120 0.5 1 1.5 2 2.5 0

34. © Digital Integrated Circuits 2nd Interconnect RI Introduced Noise M 1 X I R ` R  V f pre  V V DD V -  V ` I

35. © Digital Integrated Circuits 2nd Interconnect Power Distribution  Low-level distribution is in Metal 1  Power has to be ‘strapped’ in higher layers of metal.  The spacing is set by IR drop, electromigration, inductive effects  Always use multiple contacts on straps

36. © Digital Integrated Circuits 2nd Interconnect Power and Ground Distribution

37. © Digital Integrated Circuits 2nd Interconnect 3 Metal Layer Approach (EV4) 3rd “coarse and thick” metal layer added to the technology for EV4 design Power supplied from two sides of the die via 3rd metal layer 2nd metal layer used to form power grid 90% of 3rd metal layer used for power/clock routing Metal 3 Metal 2 Metal 1 Courtesy Compaq

38. © Digital Integrated Circuits 2nd Interconnect 4 Metal Layers Approach (EV5) 4th “coarse and thick” metal layer added to the technology for EV5 design Power supplied from four sides of the die Grid strapping done all in coarse metal 90% of 3rd and 4th metals used for power/clock routing Metal 3 Metal 2 Metal 1 Metal 4 Courtesy Compaq

39. © Digital Integrated Circuits 2nd Interconnect 2 reference plane metal layers added to the technology for EV6 design Solid planes dedicated to Vdd/Vss Significantly lowers resistance of grid Lowers on-chip inductance 6 Metal Layer Approach – EV6 Metal 4 Metal 2 Metal 1 RP2/Vdd RP1/Vss Metal 3 Courtesy Compaq

40. © Digital Integrated Circuits 2nd Interconnect Electromigration (1)

41. © Digital Integrated Circuits 2nd Interconnect Electromigration (2)

42. © Digital Integrated Circuits 2nd Interconnect Interconnect Projections: Geometry # of metal layers is steadily increasing due to: Increasing die size and device count: we need more wires and longer wires to connect everything Rising need for a hierarchical wiring network; local wires with high density and global wires with low RC 0.25  m wiring stack

43. © Digital Integrated Circuits 2nd Interconnect Interconnect Projections : Low-k dielectrics  Both delay and power are reduced by dropping interconnect capacitance  Types of low-k materials include: inorganic (SiO 2 ), organic (Polyimides) and aerogels (ultra low-k)  The numbers below are on the conservative side of the NRTS roadmap 

44. © Digital Integrated Circuits 2nd Interconnect Interconnect Projections: Copper  Copper is planned in full sub-0.25  m process flows and large-scale designs (IBM, Motorola, IEDM97)  With cladding and other effects, Cu ~ 2.2  -cm vs. 3.5 for Al(Cu)  40% reduction in resistance  Electromigration improvement; 100X longer lifetime (IBM, IEDM97)  Electromigration is a limiting factor beyond 0.18  m if Al is used (HP, IEDM95) Vias

45. © Digital Integrated Circuits 2nd Interconnect Diagonal Wiring y x destination Manhattan source diagonal 20+% Interconnect length reduction Clock speed Signal integrity Power integrity 15+% Smaller chips plus 30+% via reduction Courtesy Cadence X-initiative

46. © Digital Integrated Circuits 2nd Interconnect Clock distribution

47. © Digital Integrated Circuits 2nd Interconnect Clock Distribution Clock is distributed in a tree-like fashion H-tree

48. © Digital Integrated Circuits 2nd Interconnect More realistic H-tree [Restle98]

49. © Digital Integrated Circuits 2nd Interconnect The Grid System No rc-matching Large power

50. © Digital Integrated Circuits 2nd Interconnect Example: DEC Alpha 21164

51. © Digital Integrated Circuits 2nd Interconnect 21164 Clocking  2 phase single wire clock, distributed globally  2 distributed driver channels  Reduced RC delay/skew  Improved thermal distribution  3.75nF clock load  58 cm final driver width  Local inverters for latching  Conditional clocks in caches to reduce power  More complex race checking  Device variation t rise = 0.35ns t skew = 150ps t cycle = 3.3ns Clock waveform Location of clock driver on die pre-driver final drivers

52. © Digital Integrated Circuits 2nd Interconnect

53. © Digital Integrated Circuits 2nd Interconnect Clock Skew in Alpha Processor

54. © Digital Integrated Circuits 2nd Interconnect  2 Phase, with multiple conditional buffered clocks  2.8 nF clock load  40 cm final driver width  Local clocks can be gated “off” to save power  Reduced load/skew  Reduced thermal issues  Multiple clocks complicate race checking t rise = 0.35nst skew = 50ps t cycle = 1.67ns EV6 (Alpha 21264) Clocking 600 MHz – 0.35 micron CMOS Global clock waveform

55. © Digital Integrated Circuits 2nd Interconnect 21264 Clocking

56. © Digital Integrated Circuits 2nd Interconnect EV6 Clock Results GCLK Skew (at Vdd/2 Crossings) ps 5 10 15 20 25 30 35 40 45 50 ps 300 305 310 315 320 325 330 335 340 345 GCLK Rise Times (20% to 80% Extrapolated to 0% to 100%)

57. © Digital Integrated Circuits 2nd Interconnect EV7 Clock Hierarchy + widely dispersed drivers + DLLs compensate static and low- frequency variation + divides design and verification effort - DLL design and verification is added work + tailored clocks Active Skew Management and Multiple Clock Domains