1. L 19: Low Power Circuit Optimization

2. Power Optimization Modeling and Technology Circuit Design Level –logic Families –low-power Flip-Flops –low-power clock distribution Logic and Module Design Level Architecture and System Design Level Some Design Examples

3. Choice of Logic Family Power delay product improves as supply voltage decreases The best logic style minimizes power-delay product

4. Static CMOS Full Adder B A VDD C’ C B’ AA’ B B CC’ B B’ A B AB C C AB sum carry

5. NO Race dynamic CMOS logic(NORA) Full Adder A B C AB phi carry Phi’phi’ ABC A B C sum

6. Cascode Voltage Switch Logic(CVSL) Full Adder phi A B C’ A B C A’ B’ sumsum’ A’ B C’ phi A B’ C B Carry’Carry phi

7. Differential Cascode Voltage Switch Logic (DCVSL) A B C’ A B C A’ B’ sumsum’ A’ B C’ A B’ C B Carry’Carry

8. CMOS NonThreshold Logic(CNTL) Full Adder A B C’ A B C A’ B’ sumsum’ A’ B C’ A B’ C B Carry’Carry

9. Logic Family Full Adder Transistor Count and Area TransistorsRank Area(  m 2 ) Rank CMOS NORA CVSL DCVS CNTL 30 22 24 22 34 4 1 3 1 5 21,294 14,319 25,740 21,080 40,020 3 1 4 2 5 Simulated(ns)RankMeasured(ns)Rank CMOS NORA CVSL DCVS CNTL 46.34 45.9 45.4 61.5 54.1 3 2 1 5 4 60 47.2 49.2 72.6 87.0 3 1 2 4 5 Delays when 16-bit ripple carry adder was made

10. Logic Family Peak switching current simulated(mA)RankMeasure(mA)Rank CMOS NORA CVSL DCVS CNTL 2.42 2.74 1.08 1.19 1.25 4 5 1 2 3 1.30 1.20 1.06 1.22 1.18 5 3 1 4 2 Current(  A) Rank CMOS NORA CVSL DCVS CNTL 98 948 925 116 1320 1 4 3 2 5 Average measures current

11. AA’ZZ’ A A’ Z Z’ Q’Q AB B B’ A’ (AB)’AB Complementary Pass Transistor Logic(CPL)

12. A B B’ A’ AB (AB)’ VDD VDD-V TN High Level Degradation

13. B A B’ A’ AB B’ B A (AB)’ A’ Dual Path Transistor Logic(DPL)

14. AB B B’ A’ (AB)’ AB NMOS CPL Network O’ O Swing Restored Pass Transistor Logic(SRPL)

15. Power consumption of Flip-Flop –power consumed for the internal state change –power consumed for the clocking Because the stage change is infrequent, the clocking capacitance must be reduced. Conventional C2MOS Flip-Flop At each clock, the switched capacitance is 10MOS gates Low-Power Flip-Flops

16. Gated D Flip-Flop SSTC(Static Single-Transistor Clocked Flip-Flop DQ Clk D CK At each clock, the switched capacitance 2 MOS gates, but Slow and about 40 transistors The switched capacitance is 2 MOS gates and 16 transistors

17. Power Optimization Modeling and Technology Circuit Design Level Logic and Module Design Level –logic synthesis –module design optimization Architecture and System Design Level Some Design Examples

18. Module Design Optimization Power dissipation –layout 2um CMOS MOSIS –condition 1,000 pseudo-random input averaging the result Result –CSA has lowest power dissipation power supply current falls to zero faster Arithmetic component : Adder Adder Type Ripple Carry Carry Skip-I Carry Skip-II Carry Lookahead Carry Select Conditional Sum Delay (nsec) 54.27 28.38 21.84 17.13 19.56 20.05 Area (mm2) 0.2527 0.4492 0.5149 0.7454 1.0532 1.4784 Current (mW) 0.117 0.109 0.126 0.171 0.216 0.304 Carry Skip-I : constant block size Carry Skip-II : variable block size

19. Module Design Optimization Power estimation –conditions 50,000 random distribution input Result –wallace multiplier more attractive when operand size is large irregular layout and large layout area array multiplier –becomes unattractive as operand size increase –has higher average number of logic transitions –has much higher delay Arithmetic component : Multiplier 8b 16b 32b 8b 16b 32b Wallace Modified Array Multiplier Type 50 98 198 35 51 63 Delay(in gate)Size(gates) 567 2,405 9,918 613 2,569 10,413 Transition 583 7,348 99,102 573 3,874 19,548