1. Introduction to Sequential Logic Design Finite State-Machine Design

2. 2 Prev…FSM Analysis 1)Determine the excitation equations for the FF control inputs; (In D-FF, they are the combinational equations for D controls) 2)Substitute the excitation equations into the FF characteristic equations to obtain transition equations (Using Q* notations); 3)Use the transition equations to construct a transition table; 4)Determine the output equations; 5)Add output values to the transition table for each state to create a transition/output table; 6)Name the states and substitute state names for state- variable combinations in the transition/output table to obtain state/output table; 7)Draw a state diagram corresponding to the state/output table.

3. 3 FSM (Moore Machine) Next state= F (current state, input) Output= G (current state)

4. 4 How to Design a clocked synchronous state machine? 1)From wording description draw a desired state diagram with desired output values 2)Convert the state diagram to state/output table; 3)Use a number of state variables that is sufficient to assign unique binary codes to each state name. Substitute the state variable binary codes in the state table to make the transition table (Using Q* notations); 4)Using a flip-flop type (usually a D-FF edge triggered) for the state memory, and by the knowledge of its characteristic equation, determine the required control values for each row in the transition table. This forms the excitation table. In D-FF this is simply the substitution of Q* by D. 5)Derive excitation equations from excitation table. 6)Derive output equations 7)Draw logic diagram of the derived equations.

5. 5 Example: Using synchronous Finite State Machine, design a sequential circuit that asserts a high output (Z) for exactly two clock pulses when an input button (B) is pressed (i.e. asserted). The circuit should stay with low output, when the button (B) is not pressed (not asserted). The goal is: even if the button continues to be pressed, or vibrates due to mechanical instability, the output should be steady once asserted. Draw the state diagram, and circuit logic diagram. Use minimal number of external gates. [Hint: Use positive edge triggered D flip-flops]

6. 6 Example: Using synchronous Finite State Machine, design a sequential circuit that asserts a high output (Z) for exactly three clock pulses when an input button (B) is pressed (i.e. asserted). The circuit should stay with low output, when the button (B) is not pressed (not asserted). The goal is: even if the button continues to be pressed, or vibrates due to mechanical instability, the output should be steady once asserted. Draw the state diagram, and circuit logic diagram. Use minimal number of external gates. [Hint: Use positive edge triggered D flip-flops]

7. 7 FSM Design Example Step 1: Capture the FSM  Already done Step 2: Create architecture  2-bit state register (for 4 states)  Input b, output x  Next state signals n1, n0 Step 3: Encode the states  Any encoding will work x=1 x=0 b b’ 01 00 1011On2On1 Off On3 Inputs: b; Outputs: x Combinational logic State register s1s0 n1 n0 x b clk FSM inputs FSM outputs

8. 8 Laser Timer Example (cont.) Step 4: Create state table x=1 x=0 b b’ 01 00 1011On2On1 Off On3 Inputs: b; Outputs: x

9. 9 Laser Timer Example (cont.) Steps 5&6: Derive excitation and output equations x = s1 + s0 (note from the table that x=1 if s1 = 1 or s0 = 1) n1 = s1’.s0.b’ + s1’.s0.b + s1.s0’.b’ + s1.s0’.b n1 = s1’.s0 + s1.s0’ n0 = s1’s0’b + s1s0’b’ + s1s0’b n0 = s1’.s0’.b + s1.s0’

10. 10 FSM Design Example (cont.) Step 7: Draw circuit: combinational logic & sequential parts x = s1 + s0 n1 = s1’.s0 + s1.s0’ n0 = s1’.s0’.b + s1.s0’ n1 n0 s0 s1 clk Combinational Logic State register b FSM outputs FSM inputs x

11. 11 Understanding the FSM Behavior s0 s1 b x n1 n0 x=1 b 01 10 11 On2On1 Off On3 00 00 0 0 0 0 b’ 0 0 0 00 x=0 0 0 0 clk Inputs: Outputs: 1 0 10 b 1 0 1 0 0 s0 s1 b x n1 n0 x=1 b’ 01 1011 On2On1 Off On3 clk b x 00 00 x=0 0 0 0 state=00state=00 s0 s1 b x n1 n0 x=1 x=0 b b’ 01 00 10 11 On2On1 Off On3 1 0 1 1 0 0 0 1 1 0 clk 01 01 state=01