1. CSET 4650 Field Programmable Logic Devices Dan Solarek VHDL Additional Details & Examples

2. 2 VHDL: Modeling Styles Dataflow Most are like assigning expressions to signals Structural Define explicit components and the connections between them. Behavioral Write an algorithm that describes the circuit’s output

3. 3 VHDL: Dataflow Style Dataflow description The detail is less when compared with the structural description “Concurrent” statements include assignment and select statements Concurrency is needed to model the behavior of parallel, interconnected hardware elements Data dependencies are described, not the components and connections Includes “” and “” statements Includes “ when-else ” and “ with-select ” statements

4. 4 VHDL: Structural Style A structural description is just like the schematic A structural description is just like the schematic Includes concurrent statements Includes concurrent statements A component statement is a concurrent statement A component statement is a concurrent statement All interconnections are precisely described 2-to4 DCD V2to4dec I1 I0 EN Y0 Y1 Y2 Y3

5. 5 VHDL: Behavioral Style Behavioral description May not be synthesizable and may lead to a very large circuit Primarily used for simulation Normally uses VHDL “processes” Each VHDL process executes in parallel with other VHDL processes and concurrent statements But “sequential” statements can be used within a process

6. 6 A process can be given a unique name using an optional LABEL This is followed by the keyword process The keyword BEGIN is used to indicate the start of the process All statements within the process are executed SEQUENTIALLY. Hence, order of statements is important. A process must end with the keywords end process. TESTING: process begin TEST_VECTOR<=“00”; wait for 10 ns; TEST_VECTOR<=“01”; wait for 10 ns; TEST_VECTOR<=“10”; wait for 10 ns; TEST_VECTOR<=“11”; wait for 10 ns; end process; A process is a sequence of instructions, referred to as sequential statements. What is a PROCESS? the keyword process

7. 7 Process Sensitivity List List of signals to which the process is sensitive. Whenever there is an event on any of the signals in the sensitivity list, the process starts. Every time the process starts, it will run in its entirety. WAIT statements not allowed in a processes with a sensitivity list. label: process(sensitivity list) declaration part begin statement part end process;

8. 8 VHDL Processes Processes Describe Sequential Behavior Processes Describe Sequential Behavior Processes in VHDL Are Very Powerful Statements Processes in VHDL Are Very Powerful Statements Allow to define an arbitrary behavior that may be difficult to represent by a real circuit Allow to define an arbitrary behavior that may be difficult to represent by a real circuit Not every process can be synthesized Not every process can be synthesized Use Processes with Caution in the Code to Be Synthesized Use Processes with Caution in the Code to Be Synthesized Use Processes Freely in Testbenches Use Processes Freely in Testbenches

9. 9 VHDL Design Styles Components and interconnects structural VHDL Design Styles dataflow Concurrent statements behavioral Registers State machines Test benches Sequential statements Subset most suitable for synthesis

10. 10 VHDL Details: Design Flow VHDL compiler analyzes code for syntax errors and checks for compatibility with other modules Synthesizer converts VHDL program to a circuit with components Place and route fits the circuit to a device

11. Elements of VHDL

12. 12 Logic Operators VHDL provides the following predefined basic logic operators: Keyword and or xor xnor * nand nor not Definition conjunction inclusive or exclusive or complement exclusive or complement conjunction complement inclusive or complement * only predefined in VHDL-93

13. 13 Logic Operators (cont.) Predefined operators are all binary except for ‘not’ Multi-input operators formed from series of binary operators NAND-3:A nand B nand C Expression evaluation differs from switching algebra and, or, nand, nor are ‘short-circuit’ operators right operand not evaluated if left operand determines result

14. 14 Operator Precedence Unary ‘not’ has a higher precedence than any binary operator ALL binary operators have the SAME precedence Operators with the same precedence are evaluated left-to-right Operators in parentheses are evaluated first; innermost to outermost order Must be used for proper AND - OR evaluation

15. 15 Concurrency Software source code statements execute in page/line order (i.e., sequential order) VHDL concurrent signal assignments execute only when associated signal change value (i.e., concurrent order) page/line sequence has nothing to do with execution assignments are on a nonprocedural stimulus/ response basis (event driven) signal assignments may trigger other concurrent assignments

16. 16 Concurrent Operation Example entity XOR2_OP is port (A, B : in std_logic; Z : out std_logic); end XOR2_OP; architecture AND_OR_CONC of XOR2_OP is signal INT1, INT2: std_logic; begin Z <= INT1 or INT2; INT2 <= not A and B; INT1 <= A and not B; end AND_OR_CONC ; assignments are dependent upon each other

17. 17 Design Units and Libraries VHDL is defined such that more complex pieces are built from simpler pieces Libraries Design Units Statements Expressions Objects Types

18. 18 Design Units and Libraries (cont.) Part of a VHDL model that can be independently analyzed (error checked) is a design unit Primary Design Units Entity Declaration Package Declaration Configuration Declaration Secondary Design Units Architectural Body Package Body Primary units analyzed before secondary units

19. 19 Design Units and Libraries (cont.) Two predefined libraries in VHDL STD - contains predefined VHDL constructs such as types, objects, etc. WORK - the working library Many other libraries may exist as part of development environment IEEE library - standard types and operators needed for simulation and implementation User-defined libraries - designs for reuse Implementation specific libraries - logic families

20. Modeling Latches and Flip-Flops

21. 21 SR Latch: Structural NAND Latch R S Q t+1 0 0 U 0 1 1 1 0 0 1 1 Q t R S Q Q ENTITY latch IS PORT( R, S: IN std_logic; Q, Qbar: OUT std_logic); END ENTITY latch; ARCHITECTURE latch_arch OF latch IS BEGIN Q<= R NAND Qbar; Qbar<= S NAND Q; END ARCHITECTURE;

22. 22 SR Latch: Asynchronous ARCHITECTURE latch2_arch OF latch IS BEGIN PROCESS (R, S) BEGIN IF R = ‘0’ THEN Q <= ‘1’; Qbar <= ‘0’; ELSIF S =‘0’ THEN Q <= ‘0’; Qbar <= ‘1’; END IF; END PROCESS; END ARCHITECTURE; NAND R S Q t+1 0 0 U 0 1 1 1 0 0 1 1 Q t R S Q Q Sequential Statements Sensitivity list of signals: Every time a change of state or event occurs on these signals this process will be called

23. 23 SR Flip-Flop: Gated-Clock S R Q Q LE ARCHITECTURE Latch_arch OF GC_Latch IS BEGIN PROCESS (R, S, LE) BEGIN IF LE =‘1’ THEN IF R = ‘0’ THEN Q <= ‘1’; Qbar <= ‘0’; ELSIF S =‘0’ THEN Q <= ‘0’; Qbar <= ‘1’; END IF; END IF; END PROCESS; END ARCHITECTURE;

24. 24 Data-Flip Flops: Synchronous ARCHITECTURE Dff_arch OF Dff IS BEGIN PROCESS (Clock) BEGIN IF Clock’EVENT AND Clock=‘1’ THEN Q <= D; END IF; END PROCESS; END ARCHITECTURE; Clock’EVENT is what distinguishes a D-FlipFlip from a Latch Notice the Process does not contain D: PROCESS(Clock, D) Sensitivity lists contain signals used in conditionals (i.e., IF )

25. 25 D-Flip Flops: rising_edge ARCHITECTURE Dff_arch OF Dff IS BEGIN PROCESS (Clock) BEGIN IF Clock’EVENT AND Clock=‘1’ THEN Q <= D; END IF; END PROCESS; END ARCHITECTURE; ARCHITECTURE dff_arch OF dff IS BEGIN PROCESS (Clock) BEGIN IF rising_edge(Clock) THEN Q <= D; END IF; END PROCESS; END ARCHITECTURE; Alternate and more readable way is to use the rising_edge function

26. 26 D-Flip Flop: Asynchronous Reset ARCHITECTURE dff_reset_arch OF dff_reset IS BEGIN PROCESS (Clock, Reset) BEGIN IF Reset= ‘1’ THEN -- Asynchronous Reset Q <= ‘0’ ELSIF rising_edge(Clock) THEN --Synchronous Q <= D; END IF; END PROCESS; END ARCHITECTURE;

27. 27 D-Flip Flops: Synchronous Reset PROCESS (Clock, Reset) BEGIN IF rising_edge(Clock) THEN IF Reset=‘1’ THEN Q <= ‘0’ ELSE Q <= D; END IF; END IF; END PROCESS; Synchronous Reset Synchronous FF PROCESS (Clock, Reset) BEGIN IF Reset=‘1’ THEN Q <= ‘0’ ELSIF rising_edge(Clock) THEN Q <= D; END IF; END PROCESS; Asynchronous Reset Synchronous FF

28. 28 D-Flip Flop: Async. Reset & Preset PROCESS (Clock, Reset, Preset) BEGIN IF Reset=‘1’ THEN --highest priority Q <= ‘0’; ELSIF Preset=‘1’ THEN Q <= ‘0’; ELSIF rising_edge(Clock) THEN Q <= D; END IF; END PROCESS;

29. Vector operations and conditional concurrent signal assignments

30. 30 Bit Vectors Signals can be more than one bit (a vector) Represent  P address and data, function selection, etc. Declaration is similar to single bit signals type is bit_vector or std_logic_vector We also must specify vector index range and direction big endian: (low to high) little endian: (high downto low)

31. 31 Vector Declarations port ( A, B: in std_logic_vector(7 downto 0); Z: out std_logic_vector(1 to 16) ); A and B : Z : 123456789 76543210 10111213141516 Note! The first bit and last bit index numbers define the number of bits in the vector (i.e., max - min + 1)

32. 32 Vector Literals Single bit binary literals are ‘0’ and ‘1’ Vector binary literals are “0101”, “10_01” literal values may have an underscore embedded to improve readability

33. 33 Vector Logical Operations Single bit logical operations also apply to vectors Operands MUST be the same size (generally applies to all vector operations) Assignment target must also have the same number of bits as the result Operations are applied bitwise to operands to produce the vector result

34. 34 Vector Operations Given: Signal A, B, Z: std_logic_vector(7 downto 0); Then the following logical operation and assignment Z <= A and B; Is equivalent to: for i = 0 to 7 Z i = A i and B i ;

35. 35 Vector Arithmetic Operations Vector arithmetic operations are basically the same as vector logical operations Operands MUST be the same size Assignment target must also have the same number of bits as the result Operations are applied bitwise to operands to produce the vector result The only difference is the carry or borrow Carry in/out must be specially handled Result can be 1 bit larger than operands (CO)

36. 36 4-bit Adder (Dataflow VHDL) entity add4 is port (a, b: in std_logic_vector (3 downto 0); cin: in std_logic; cout: out std_logic; s: out std_logic_vector(3 downto 0) ); end add4; architecture df of add4 is signal tmpsum std_logic_vector(4 downto 0); begin tmpsum <= (‘0’ & a) + (‘0’ & b) + (“0000” & cin); s <= tmpsum(3 downto 0); cout <= tmpsum(4); end df;

37. 37 Add4 Example In the previous example note: The “&” symbol is the concatenation operator joins operands together so that result length is sum of lengths of operands. joins operands together so that result length is sum of lengths of operands. In order to be able to access the MSB carry out we had to add 5-bit values (used & operator to add leading zeros to operands) To assign result to S, we had to access only the least significant 4 bits of S; this is a SLICE The carry out is a single bit assignment of the LSB of the result

38. 38 Vectors and Concatenation signal A: std_logic_vector(3 downto 0); signal B: std_logic_vector(3 downto 0); signal C, D, E: std_logic_vector(7 downto 0); A <= ”0000”; B <= ”1111”; C <= A & B; -- C = ”00001111” D <= ‘0’ & ”0001111”; -- D <= ”00001111” E <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ & ‘1’ & ‘1’; -- E <= ”00001111”

39. 39 Slice Reference & Assignment A slice is a part of a vector accessed by a range clause (hi downto lo) or (lo to hi) indexes cannot go out of bounds of original declaration range direction must be the same as the original vector a single index is use to access a single bit e.g., tmpsum(4); assignee must be the same size as the slice cout <= tmpsum(4);

40. 40 Conditional Concurrent Assignment Up to now, signal assignment has been only based on evaluation of operand changes expressions are boolean algebra only hard to understand what is being implemented e.g., a 4-to-1 MUX: Z <= (a and not s(1) and not s(0)) or (b and not s(1) and s(0)) or (c and s(1) and not s(0)) or (d and s(1) or s(0));

41. 41 Conditional Concurrent Assignment General Form: target_signal <= value1 when cond1 else value2 when cond2 else * valuem when condm else valuen; Note that the condition clauses must evaluate to a logical expression.

42. 42 4-to-1 Mux (Cond. Concurrent Form) Z <= A when s = “00” else B when s = “01” else C when s = “10” else D; Note that in the last case, we did not specify a condition; this is the “when no other condition is met” case. Note also that we can conditionalize the last case by if so, we must ensure that all possible condition combinations are addressed.

43. 43 Relational Operators In the previous example we introduced a new operator, the relational “equals” The relational operators are = (equals)/= (not equals) > (greater than) (greater than)< (less than) >= (greater or equal) = (greater or equal)<= (less or equal) Note that <= (less or equal) is same operator as <= (signal assignment); i.e., context dependent Precedence of relational operators is between “not” and the other logical operators.

44. 44 Selected Signal Assignment Another form of concurrent signal assignment is the Select assignment Similar to a software CASE statement we first identify the “discriminator” signal or expression we will test values and associated conditions are then identified Like conditional signal assignment we must ensure that all cases of discriminator are covered “others” condition makes this easy

45. 45 Selected Signal Assignment General Form: WITH discriminator SELECT target_signal <= value1 WHEN choices1, value2 WHEN choices2, * valuem WHEN choicesm, valuen WHEN others; The “choices” are values of the discriminator; either single, multiple or a range.

46. 46 Selected Signal Assignment All possible values of the discriminator must be covered single value: when “0001”, multiple values: when “0100” | “0110” | “1000”, value range: when“1010” to “1111”, everything else: when others; The last case “ when others ” must be the last clause if used Comma separates clauses, semicolon ends the statement OR

47. 47 Selected Signal Assignment WITH digit SELECT segs <= “1110111” when “0000”, “0010010” when “0001”, “1011101” when “0010”, “1011011” when “0011”, “0111010” when “0100”, “1101011” when “0101”, “0101111” when “0110”, “1010010” when “0111”, “1111111” when “1000”, “1111010” when “1001”, “1101101” when others;

48. 48 Vector Attributes Attributes allow access to signal definition information useful when designing generic VHDL tells use range, index, length of a signal General form is signal_name’attr_name Some attributes are pre-defined

49. 49 Pre-defined Attributes Name ‘left ‘right ‘high ‘low ‘range ‘reverse_range ‘length Definition index value on left of range index value on right of range greatest index value of range least index value of range range expression if signal reversed signal range expression number of bits in range

50. 50 Pre-Defined Attributes Attribute ex‘left ex‘right ex‘high ex‘low ex‘range ex‘reverse_range ex‘length Value 11 8 11 8 (11 downto 8) (8 to 11) 4 signal ex std_logic_vector(11 downto 8);

51. Latches, Flip-Flops and Registers

52. 52 ClockD 0 1 1 – 0 1 0 1 Truth Table Graphical Symbol t 1 t 2 t 3 t 4 Time Clock D Q Timing Diagram Q(t+1) Q(t) Data Latch D Q Clock

53. 53 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY latch IS PORT ( D, Clock : IN STD_LOGIC; Q : OUT STD_LOGIC); END latch; ARCHITECTURE Behavior OF latch IS BEGIN PROCESS ( D, Clock ) BEGIN IF Clock = '1' THEN Q <= D; END IF; END PROCESS; END Behavior; Data Latch D Q Clock

54. 54 Clk D   0 1 0 1 Truth Table t 1 t 2 t 3 t 4 Time Clock D Q Timing Diagram Q(t+1) Q(t) Data Flip-Flop D Q Clock Graphical Symbol 0 – Q(t) 1 –

55. 55 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC; Q : OUT STD_LOGIC); END flipflop; ARCHITECTURE Behavior_1 OF flipflop IS BEGIN PROCESS ( Clock ) BEGIN IF Clock'EVENT AND Clock = '1' THEN Q <= D; END IF; END PROCESS; END Behavior_1; Data Flip-Flop D Q Clock

56. 56 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior_2 OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; Q <= D ; END PROCESS ; END Behavior_2 ; Data Flip-Flop D Q Clock

57. 57 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= '0' ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; Data Flip-Flop: Asynchronous Reset D Q Clock Resetn

58. 58 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC; Q : OUT STD_LOGIC); END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF Resetn = '0' THEN Q <= '0' ; ELSE Q <= D ; END IF ; END PROCESS ; END Behavior ; Data Flip-Flop: Synchronous Reset D Q Clock Resetn

59. 59 8-Bit Register: Asynchronous Reset LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY reg8 IS PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ; END reg8 ; ARCHITECTURE Behavior OF reg8 IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= "00000000" ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ;` Resetn Clock reg8 88 DQ

60. 60 N-Bit Register: Asynchronous Reset LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY regn IS GENERIC ( N : INTEGER := 16 ) ; PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regn ; ARCHITECTURE Behavior OF regn IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q '0') ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; Resetn Clock regn NN DQ

61. 61 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY regn IS GENERIC ( N : INTEGER := 8 ) ; PORT (D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regn ; ARCHITECTURE Behavior OF regn IS BEGIN PROCESS (Clock) BEGIN IF (Clock'EVENT AND Clock = '1' ) THEN IF Enable = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; N-Bit Register With Enable Q D Enable Clock regn NN