1. CE1110: Digital Logic Design Sequential Circuits

20. Design a FSM that detects 3 or more consecutive ones from a serial input x. Design Example X Y 3 ones detector Steps: 1. Understand the statement of the Specification 2. Obtain a state diagram of the FSM from the specification 3. Perform state assignment 4. Determine the number of flip flop(to represent 4 s tates => 2 flip flops) 5. Choose type of flip-flop if not given (for example we will choose D-FF)

21. 1. Derive state diagram S0 00 S1 01 1/0 0/0 We will begin with assumption that no input entered to system, we will give this state name S 0 Our system will stop at S 0 if the input to the system is always ‘0’ If the system has ‘1’ input a new states created which represent the state that you have only 1 we will call it S1 Input/Output

22. If the system was in state S1 and a ‘0’ entered the system, it must be returned to S 0 as we are searching for 3 consecutive ones. Else if another ‘1’ entered the system it will go to new state that represent existing of two ones consecutive we will call it S 2. If the system was in state S2 and ‘0’ entered the system it will return to S0. Else if ‘1’ entered to the system it will move to a new state that represent the existing of three consecutive ones S3 and the output would be equal to y=‘1’. If the system has more ones as an input it will continue at S3 and output y=‘1’ Finally, if we have input X=‘0’ to the system, it will goes to the starting state S0 0/0 S0 00 S1 01 S2 10 0/0 1/0 1/1 S3 11 0/0 1/1

23. Present State InputNext State Out FF Inputs ABXAByDADB 00000000 00101001 01000000 01110010 10000000 10111111 11000000 11111111 2. Construct the state table Q(t)Q(t+1)D 000 011 100 111 D–FF Excitation Table

24. 3. Drive simplified State Equations Note: Output here depends on the present state (A(t)) and input (x)

25. 4: Implement the FSM

26. Sequential Circuit Analysis (cont.) –Generate State Diagram Circles (nodes) represent current or present state values Lines (arcs) represent how state and output values change –Given the current state and current inputs, the next state and output values are indicated by the associated arc State diagram can have different forms depending on the type of sequential circuit output. Present State Value Next State Value Inputs/outputs

27. 27 Example Analyze the following sequential circuit How to analyze any sequential circuit You need to know : –State equation –State diagram –State table

28. 1- Determine State equation From the circuit get the logic equations of the input of flip-flops A(t+1) & B(t+1) and output y(t) FF input equations A(t+1) = A(t)X(t)+B(t)X(t) B(t+1) = A’(t)X(t) Output equation Y(t) = X’(t)(B(t)+A(t)) A(t+1) B(t+1) (t)

29. 2-Create State table From logic equation & characteristics table of flip-flop create State table FF input equations A(t+1) = AX+BX B(t+1) = A’X Output equation Y = X’(B+A) D flip-flop characteristic table

30. 3-Construct the state diagram 0010 0111 0/0 Input/Output 1/00/1 1/0 0/1 1/0 0/1 1/0

31. Registers There are also another applications for Flip-flops like Registers –“Register” is a small amount of storage available on the CPU whose contents can be accessed more quickly than storage available elsewhere. Typically, this specialized storage is not considered part of the normal memory range for the machine.storage CPU –Registers are normally measured by the number of bits they can hold (ex. 8-bits or 32-bits register)bits –They have been implemented using individual flip-flopsflip-flops

32. What’s the main structure of the register from inside? And what’s the types of registers?

33. Registers  An n-bit register consists of a group n flip -flops capable o f storing n bits of binary info.  All Flip-flops are connected to one clock source  Each flip-flop can store one bit of Info.  Clear signal during normal operation is set to high  The clear input is useful for clearing all the content of the register to all 0’s  Problem: Typically don’t want to load every clock  Solution: use a external signal to control the operation of the load

34. Registers with Parallel Load 1 1 0 0 0 1

35. Shift Registers  A register capable of shifting its binary information in one or both direction is called a shift register  A chain of flip-flops in cascade 010 SI CLK Qa Qb etc 0 Qa QbQc

36. Universal Shift Registers S1S2Action 00No Change 01Shift Right 10Shift Left 11Parallel Load  No Change  Shift Right  Shift Left  Parallel Load  Need a Clear and Clock